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clocksource: new RISC-V SBI timer driver
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra <atish.patra@wdc.com>. Signed-off-by: Dmitriy Cherkasov <dmitriy@oss-tech.org> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> [hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(), minor cleanups, merged hotplug cpu support and other improvements from Atish] Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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‎arch/riscv/include/asm/smp.h

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@@ -24,9 +24,6 @@
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#ifdef CONFIG_SMP
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/* SMP initialization hook for setup_arch */
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void __init init_clockevent(void);
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/* SMP initialization hook for setup_arch */
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void __init setup_smp(void);
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‎arch/riscv/kernel/irq.c

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@@ -30,6 +30,9 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs, unsigned long cause)
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irq_enter();
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switch (cause & ~INTERRUPT_CAUSE_FLAG) {
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case INTERRUPT_CAUSE_TIMER:
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riscv_timer_interrupt();
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break;
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#ifdef CONFIG_SMP
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case INTERRUPT_CAUSE_SOFTWARE:
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/*

‎arch/riscv/kernel/smpboot.c

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@@ -104,7 +104,6 @@ asmlinkage void __init smp_callin(void)
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current->active_mm = mm;
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trap_init();
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init_clockevent();
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notify_cpu_starting(smp_processor_id());
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set_cpu_online(smp_processor_id(), 1);
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local_flush_tlb_all();

‎arch/riscv/kernel/time.c

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@@ -18,12 +18,6 @@
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unsigned long riscv_timebase;
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void __init init_clockevent(void)
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{
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timer_probe();
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csr_set(sie, SIE_STIE);
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}
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void __init time_init(void)
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{
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struct device_node *cpu;
@@ -35,6 +29,5 @@ void __init time_init(void)
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riscv_timebase = prop;
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lpj_fine = riscv_timebase / HZ;
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init_clockevent();
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timer_probe();
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}

‎drivers/clocksource/Kconfig

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@@ -609,4 +609,15 @@ config ATCPIT100_TIMER
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help
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This option enables support for the Andestech ATCPIT100 timers.
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config RISCV_TIMER
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bool "Timer for the RISC-V platform"
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depends on RISCV
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default y
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select TIMER_PROBE
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select TIMER_OF
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help
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This enables the per-hart timer built into all RISC-V systems, which
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is accessed via both the SBI and the rdcycle instruction. This is
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required for all RISC-V systems.
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endmenu

‎drivers/clocksource/Makefile

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@@ -78,3 +78,4 @@ obj-$(CONFIG_H8300_TPU) += h8300_tpu.o
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obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
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obj-$(CONFIG_X86_NUMACHIP) += numachip.o
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obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o
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obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o

‎drivers/clocksource/riscv_timer.c

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@@ -0,0 +1,105 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <asm/sbi.h>
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/*
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* All RISC-V systems have a timer attached to every hart. These timers can be
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* read by the 'rdcycle' pseudo instruction, and can use the SBI to setup
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* events. In order to abstract the architecture-specific timer reading and
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* setting functions away from the clock event insertion code, we provide
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* function pointers to the clockevent subsystem that perform two basic
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* operations: rdtime() reads the timer on the current CPU, and
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* next_event(delta) sets the next timer event to 'delta' cycles in the future.
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* As the timers are inherently a per-cpu resource, these callbacks perform
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* operations on the current hart. There is guaranteed to be exactly one timer
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* per hart on all RISC-V systems.
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*/
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static int riscv_clock_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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csr_set(sie, SIE_STIE);
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sbi_set_timer(get_cycles64() + delta);
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return 0;
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}
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static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
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.name = "riscv_timer_clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 100,
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.set_next_event = riscv_clock_next_event,
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};
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/*
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* It is guaranteed that all the timers across all the harts are synchronized
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* within one tick of each other, so while this could technically go
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* backwards when hopping between CPUs, practically it won't happen.
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*/
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static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
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{
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return get_cycles64();
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}
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static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
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.name = "riscv_clocksource",
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.rating = 300,
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.mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.read = riscv_clocksource_rdtime,
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};
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static int riscv_timer_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
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ce->cpumask = cpumask_of(cpu);
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clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
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csr_set(sie, SIE_STIE);
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return 0;
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}
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static int riscv_timer_dying_cpu(unsigned int cpu)
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{
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csr_clear(sie, SIE_STIE);
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return 0;
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}
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/* called directly from the low-level interrupt handler */
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void riscv_timer_interrupt(void)
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{
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struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
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csr_clear(sie, SIE_STIE);
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evdev->event_handler(evdev);
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}
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static int __init riscv_timer_init_dt(struct device_node *n)
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{
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int cpu_id = riscv_of_processor_hart(n), error;
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struct clocksource *cs;
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if (cpu_id != smp_processor_id())
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return 0;
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cs = per_cpu_ptr(&riscv_clocksource, cpu_id);
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clocksource_register_hz(cs, riscv_timebase);
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error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
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"clockevents/riscv/timer:starting",
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riscv_timer_starting_cpu, riscv_timer_dying_cpu);
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if (error)
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pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
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error, cpu_id);
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return error;
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}
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TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);

‎include/linux/cpuhotplug.h

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@@ -125,6 +125,7 @@ enum cpuhp_state {
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CPUHP_AP_MARCO_TIMER_STARTING,
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CPUHP_AP_MIPS_GIC_TIMER_STARTING,
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CPUHP_AP_ARC_TIMER_STARTING,
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CPUHP_AP_RISCV_TIMER_STARTING,
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CPUHP_AP_KVM_STARTING,
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CPUHP_AP_KVM_ARM_VGIC_INIT_STARTING,
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CPUHP_AP_KVM_ARM_VGIC_STARTING,

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