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Benjamin-GaignardBenjamin-Gaignard
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Merge remote-tracking branch 'media_tree/vsp1' into generic-zpos-v8
2 parents a1f5524 + 894dde5 commit 62c2cd0

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‎Documentation/DocBook/media/v4l/media-types.xml

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,70 @@
121121
<entry><constant>MEDIA_ENT_F_AUDIO_MIXER</constant></entry>
122122
<entry>Audio Mixer Function Entity.</entry>
123123
</row>
124+
<row>
125+
<entry><constant>MEDIA_ENT_F_PROC_VIDEO_COMPOSER</constant></entry>
126+
<entry>Video composer (blender). An entity capable of video
127+
composing must have at least two sink pads and one source
128+
pad, and composes input video frames onto output video
129+
frames. Composition can be performed using alpha blending,
130+
color keying, raster operations (ROP), stitching or any other
131+
means.
132+
</entry>
133+
</row>
134+
<row>
135+
<entry><constant>MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER</constant></entry>
136+
<entry>Video pixel formatter. An entity capable of pixel formatting
137+
must have at least one sink pad and one source pad. Read
138+
pixel formatters read pixels from memory and perform a subset
139+
of unpacking, cropping, color keying, alpha multiplication
140+
and pixel encoding conversion. Write pixel formatters perform
141+
a subset of dithering, pixel encoding conversion and packing
142+
and write pixels to memory.
143+
</entry>
144+
</row>
145+
<row>
146+
<entry><constant>MEDIA_ENT_F_PROC_VIDEO_PIXEL_ENC_CONV</constant></entry>
147+
<entry>Video pixel encoding converter. An entity capable of pixel
148+
enconding conversion must have at least one sink pad and one
149+
source pad, and convert the encoding of pixels received on
150+
its sink pad(s) to a different encoding output on its source
151+
pad(s). Pixel encoding conversion includes but isn't limited
152+
to RGB to/from HSV, RGB to/from YUV and CFA (Bayer) to RGB
153+
conversions.
154+
</entry>
155+
</row>
156+
<row>
157+
<entry><constant>MEDIA_ENT_F_PROC_VIDEO_LUT</constant></entry>
158+
<entry>Video look-up table. An entity capable of video lookup table
159+
processing must have one sink pad and one source pad. It uses
160+
the values of the pixels received on its sink pad to look up
161+
entries in internal tables and output them on its source pad.
162+
The lookup processing can be performed on all components
163+
separately or combine them for multi-dimensional table
164+
lookups.
165+
</entry>
166+
</row>
167+
<row>
168+
<entry><constant>MEDIA_ENT_F_PROC_VIDEO_SCALER</constant></entry>
169+
<entry>Video scaler. An entity capable of video scaling must have
170+
at least one sink pad and one source pad, and scale the
171+
video frame(s) received on its sink pad(s) to a different
172+
resolution output on its source pad(s). The range of
173+
supported scaling ratios is entity-specific and can differ
174+
between the horizontal and vertical directions (in particular
175+
scaling can be supported in one direction only). Binning and
176+
skipping are considered as scaling.
177+
</entry>
178+
</row>
179+
<row>
180+
<entry><constant>MEDIA_ENT_F_PROC_VIDEO_STATISTICS</constant></entry>
181+
<entry>Video statistics computation (histogram, 3A, ...). An entity
182+
capable of statistics computation must have one sink pad and
183+
one source pad. It computes statistics over the frames
184+
received on its sink pad and outputs the statistics data on
185+
its source pad.
186+
</entry>
187+
</row>
124188
</tbody>
125189
</tgroup>
126190
</table>

‎Documentation/devicetree/bindings/media/mediatek-vpu.txt

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
* Mediatek Video Processor Unit
2+
3+
Video Processor Unit is a HW video controller. It controls HW Codec including
4+
H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).
5+
6+
Required properties:
7+
- compatible: "mediatek,mt8173-vpu"
8+
- reg: Must contain an entry for each entry in reg-names.
9+
- reg-names: Must include the following entries:
10+
"tcm": tcm base
11+
"cfg_reg": Main configuration registers base
12+
- interrupts: interrupt number to the cpu.
13+
- clocks : clock name from clock manager
14+
- clock-names: must be main. It is the main clock of VPU
15+
16+
Optional properties:
17+
- memory-region: phandle to a node describing memory (see
18+
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
19+
to be used for VPU extended memory; if not present, VPU may be located
20+
anywhere in the memory
21+
22+
Example:
23+
vpu: vpu@10020000 {
24+
compatible = "mediatek,mt8173-vpu";
25+
reg = <0 0x10020000 0 0x30000>,
26+
<0 0x10050000 0 0x100>;
27+
reg-names = "tcm", "cfg_reg";
28+
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
29+
clocks = <&topckgen TOP_SCP_SEL>;
30+
clock-names = "main";
31+
};

‎Documentation/devicetree/bindings/media/renesas,fcp.txt

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
Renesas R-Car Frame Compression Processor (FCP)
2+
-----------------------------------------------
3+
4+
The FCP is a companion module of video processing modules in the Renesas R-Car
5+
Gen3 SoCs. It provides data compression and decompression, data caching, and
6+
conversion of AXI transactions in order to reduce the memory bandwidth.
7+
8+
There are three types of FCP: FCP for Codec (FCPC), FCP for VSP (FCPV) and FCP
9+
for FDP (FCPF). Their configuration and behaviour depend on the module they
10+
are paired with. These DT bindings currently support the FCPV only.
11+
12+
- compatible: Must be one or more of the following
13+
14+
- "renesas,r8a7795-fcpv" for R8A7795 (R-Car H3) compatible 'FCP for VSP'
15+
- "renesas,fcpv" for generic compatible 'FCP for VSP'
16+
17+
When compatible with the generic version, nodes must list the
18+
SoC-specific version corresponding to the platform first, followed by the
19+
family-specific and/or generic versions.
20+
21+
- reg: the register base and size for the device registers
22+
- clocks: Reference to the functional clock
23+
24+
25+
Device node example
26+
-------------------
27+
28+
fcpvd1: fcp@fea2f000 {
29+
compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
30+
reg = <0 0xfea2f000 0 0x200>;
31+
clocks = <&cpg CPG_MOD 602>;
32+
};

‎Documentation/devicetree/bindings/media/renesas,vsp1.txt

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,11 @@ Required properties:
1414
- interrupts: VSP interrupt specifier.
1515
- clocks: A phandle + clock-specifier pair for the VSP functional clock.
1616

17+
Optional properties:
18+
19+
- renesas,fcp: A phandle referencing the FCP that handles memory accesses
20+
for the VSP. Not needed on Gen2, mandatory on Gen3.
21+
1722

1823
Example: R8A7790 (R-Car H2) VSP1-S node
1924

‎Documentation/devicetree/bindings/media/s5p-mfc.txt

Lines changed: 31 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -21,15 +21,18 @@ Required properties:
2121
- clock-names : from common clock binding: must contain "mfc",
2222
corresponding to entry in the clocks property.
2323

24-
- samsung,mfc-r : Base address of the first memory bank used by MFC
25-
for DMA contiguous memory allocation and its size.
26-
27-
- samsung,mfc-l : Base address of the second memory bank used by MFC
28-
for DMA contiguous memory allocation and its size.
29-
3024
Optional properties:
3125
- power-domains : power-domain property defined with a phandle
3226
to respective power domain.
27+
- memory-region : from reserved memory binding: phandles to two reserved
28+
memory regions, first is for "left" mfc memory bus interfaces,
29+
second if for the "right" mfc memory bus, used when no SYSMMU
30+
support is available
31+
32+
Obsolete properties:
33+
- samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region
34+
property instead
35+
3336

3437
Example:
3538
SoC specific DT entry:
@@ -43,9 +46,29 @@ mfc: codec@13400000 {
4346
clock-names = "mfc";
4447
};
4548

49+
Reserved memory specific DT entry for given board (see reserved memory binding
50+
for more information):
51+
52+
reserved-memory {
53+
#address-cells = <1>;
54+
#size-cells = <1>;
55+
ranges;
56+
57+
mfc_left: region@51000000 {
58+
compatible = "shared-dma-pool";
59+
no-map;
60+
reg = <0x51000000 0x800000>;
61+
};
62+
63+
mfc_right: region@43000000 {
64+
compatible = "shared-dma-pool";
65+
no-map;
66+
reg = <0x43000000 0x800000>;
67+
};
68+
};
69+
4670
Board specific DT entry:
4771

4872
codec@13400000 {
49-
samsung,mfc-r = <0x43000000 0x800000>;
50-
samsung,mfc-l = <0x51000000 0x800000>;
73+
memory-region = <&mfc_left>, <&mfc_right>;
5174
};

‎MAINTAINERS

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7357,6 +7357,16 @@ L: linux-iio@vger.kernel.org
73577357
S: Maintained
73587358
F: drivers/iio/potentiometer/mcp4531.c
73597359

7360+
MEDIA DRIVERS FOR RENESAS - FCP
7361+
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
7362+
L: linux-media@vger.kernel.org
7363+
L: linux-renesas-soc@vger.kernel.org
7364+
T: git git://linuxtv.org/media_tree.git
7365+
S: Supported
7366+
F: Documentation/devicetree/bindings/media/renesas,fcp.txt
7367+
F: drivers/media/platform/rcar-fcp.c
7368+
F: include/media/rcar-fcp.h
7369+
73607370
MEDIA DRIVERS FOR RENESAS - VSP1
73617371
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
73627372
L: linux-media@vger.kernel.org
@@ -7366,8 +7376,18 @@ S: Supported
73667376
F: Documentation/devicetree/bindings/media/renesas,vsp1.txt
73677377
F: drivers/media/platform/vsp1/
73687378

7379+
MEDIA DRIVERS FOR HELENE
7380+
M: Abylay Ospan <aospan@netup.ru>
7381+
L: linux-media@vger.kernel.org
7382+
W: https://linuxtv.org
7383+
W: http://netup.tv/
7384+
T: git git://linuxtv.org/media_tree.git
7385+
S: Supported
7386+
F: drivers/media/dvb-frontends/helene*
7387+
73697388
MEDIA DRIVERS FOR ASCOT2E
73707389
M: Sergey Kozlov <serjk@netup.ru>
7390+
M: Abylay Ospan <aospan@netup.ru>
73717391
L: linux-media@vger.kernel.org
73727392
W: https://linuxtv.org
73737393
W: http://netup.tv/
@@ -7377,6 +7397,7 @@ F: drivers/media/dvb-frontends/ascot2e*
73777397

73787398
MEDIA DRIVERS FOR CXD2841ER
73797399
M: Sergey Kozlov <serjk@netup.ru>
7400+
M: Abylay Ospan <aospan@netup.ru>
73807401
L: linux-media@vger.kernel.org
73817402
W: https://linuxtv.org
73827403
W: http://netup.tv/
@@ -7386,6 +7407,7 @@ F: drivers/media/dvb-frontends/cxd2841er*
73867407

73877408
MEDIA DRIVERS FOR HORUS3A
73887409
M: Sergey Kozlov <serjk@netup.ru>
7410+
M: Abylay Ospan <aospan@netup.ru>
73897411
L: linux-media@vger.kernel.org
73907412
W: https://linuxtv.org
73917413
W: http://netup.tv/
@@ -7395,6 +7417,7 @@ F: drivers/media/dvb-frontends/horus3a*
73957417

73967418
MEDIA DRIVERS FOR LNBH25
73977419
M: Sergey Kozlov <serjk@netup.ru>
7420+
M: Abylay Ospan <aospan@netup.ru>
73987421
L: linux-media@vger.kernel.org
73997422
W: https://linuxtv.org
74007423
W: http://netup.tv/
@@ -7404,6 +7427,7 @@ F: drivers/media/dvb-frontends/lnbh25*
74047427

74057428
MEDIA DRIVERS FOR NETUP PCI UNIVERSAL DVB devices
74067429
M: Sergey Kozlov <serjk@netup.ru>
7430+
M: Abylay Ospan <aospan@netup.ru>
74077431
L: linux-media@vger.kernel.org
74087432
W: https://linuxtv.org
74097433
W: http://netup.tv/
@@ -7653,10 +7677,8 @@ L: linux-media@vger.kernel.org
76537677
W: https://linuxtv.org
76547678
W: http://palosaari.fi/linux/
76557679
Q: http://patchwork.linuxtv.org/project/linux-media/list/
7656-
T: git git://linuxtv.org/anttip/media_tree.git
76577680
S: Maintained
7658-
F: drivers/staging/media/mn88472/
7659-
F: drivers/media/dvb-frontends/mn88472.h
7681+
F: drivers/media/dvb-frontends/mn88472*
76607682

76617683
MN88473 MEDIA DRIVER
76627684
M: Antti Palosaari <crope@iki.fi>

‎drivers/gpu/drm/rcar-du/rcar_du_vsp.c

Lines changed: 25 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -148,40 +148,39 @@ static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane)
148148
struct rcar_du_vsp_plane_state *state =
149149
to_rcar_vsp_plane_state(plane->plane.state);
150150
struct drm_framebuffer *fb = plane->plane.state->fb;
151-
struct v4l2_rect src;
152-
struct v4l2_rect dst;
153-
dma_addr_t paddr[2] = { 0, };
154-
u32 pixelformat = 0;
151+
struct vsp1_du_atomic_config cfg = {
152+
.pixelformat = 0,
153+
.pitch = fb->pitches[0],
154+
.alpha = state->alpha,
155+
.zpos = state->zpos,
156+
};
155157
unsigned int i;
156158

157-
src.left = state->state.src_x >> 16;
158-
src.top = state->state.src_y >> 16;
159-
src.width = state->state.src_w >> 16;
160-
src.height = state->state.src_h >> 16;
159+
cfg.src.left = state->state.src_x >> 16;
160+
cfg.src.top = state->state.src_y >> 16;
161+
cfg.src.width = state->state.src_w >> 16;
162+
cfg.src.height = state->state.src_h >> 16;
161163

162-
dst.left = state->state.crtc_x;
163-
dst.top = state->state.crtc_y;
164-
dst.width = state->state.crtc_w;
165-
dst.height = state->state.crtc_h;
164+
cfg.dst.left = state->state.crtc_x;
165+
cfg.dst.top = state->state.crtc_y;
166+
cfg.dst.width = state->state.crtc_w;
167+
cfg.dst.height = state->state.crtc_h;
166168

167169
for (i = 0; i < state->format->planes; ++i) {
168170
struct drm_gem_cma_object *gem;
169171

170172
gem = drm_fb_cma_get_gem_obj(fb, i);
171-
paddr[i] = gem->paddr + fb->offsets[i];
173+
cfg.mem[i] = gem->paddr + fb->offsets[i];
172174
}
173175

174176
for (i = 0; i < ARRAY_SIZE(formats_kms); ++i) {
175177
if (formats_kms[i] == state->format->fourcc) {
176-
pixelformat = formats_v4l2[i];
178+
cfg.pixelformat = formats_v4l2[i];
177179
break;
178180
}
179181
}
180182

181-
WARN_ON(!pixelformat);
182-
183-
vsp1_du_atomic_update(plane->vsp->vsp, plane->index, pixelformat,
184-
fb->pitches[0], paddr, &src, &dst);
183+
vsp1_du_atomic_update(plane->vsp->vsp, plane->index, &cfg);
185184
}
186185

187186
static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane,
@@ -220,8 +219,7 @@ static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane,
220219
if (plane->state->crtc)
221220
rcar_du_vsp_plane_setup(rplane);
222221
else
223-
vsp1_du_atomic_update(rplane->vsp->vsp, rplane->index, 0, 0, 0,
224-
NULL, NULL);
222+
vsp1_du_atomic_update(rplane->vsp->vsp, rplane->index, NULL);
225223
}
226224

227225
static const struct drm_plane_helper_funcs rcar_du_vsp_plane_helper_funcs = {
@@ -269,6 +267,7 @@ static void rcar_du_vsp_plane_reset(struct drm_plane *plane)
269267
return;
270268

271269
state->alpha = 255;
270+
state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1;
272271

273272
plane->state = &state->state;
274273
plane->state->plane = plane;
@@ -283,6 +282,8 @@ static int rcar_du_vsp_plane_atomic_set_property(struct drm_plane *plane,
283282

284283
if (property == rcdu->props.alpha)
285284
rstate->alpha = val;
285+
else if (property == rcdu->props.zpos)
286+
rstate->zpos = val;
286287
else
287288
return -EINVAL;
288289

@@ -299,6 +300,8 @@ static int rcar_du_vsp_plane_atomic_get_property(struct drm_plane *plane,
299300

300301
if (property == rcdu->props.alpha)
301302
*val = rstate->alpha;
303+
else if (property == rcdu->props.zpos)
304+
*val = rstate->zpos;
302305
else
303306
return -EINVAL;
304307

@@ -378,6 +381,8 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp)
378381

379382
drm_object_attach_property(&plane->plane.base,
380383
rcdu->props.alpha, 255);
384+
drm_object_attach_property(&plane->plane.base,
385+
rcdu->props.zpos, 1);
381386
}
382387

383388
return 0;

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