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Merge tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM new SoC family support from Arnd Bergmann: "Two new SoC families are added this time. Sugaya Taichi submitted support for the Milbeaut SoC family from Socionext and explains: "SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for computer vision. It also features advanced functionalities such as 360-degree, real-time spherical stitching with multi cameras, image stabilization for without mechanical gimbals, and rolling shutter correction. More detail is below: https://www.socionext.com/en/products/assp/milbeaut/SC2000.html" Interestingly, this one has a history dating back to older chips made by Socionext and previously Matsushita/Panasonic based on their own mn10300 CPU architecture that was removed from the kernel last year. Manivannan Sadhasivam adds support for another SoC family, this is the Bitmain BM1880 chip used in the Sophon Edge TPU developer board. The chip is intended for Deep Learning applications, and comes with dual-core Arm Cortex-A53 to run Linux as well as a RISC-V microcontroller core to control the tensor unit. For the moment, the TPU is not accessible in mainline Linux, so we treat it as a generic Arm SoC. More information is available at https://www.sophon.ai/" * tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: ARM: multi_v7_defconfig: add ARCH_MILBEAUT and ARCH_MILBEAUT_M10V ARM: configs: Add Milbeaut M10V defconfig ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs dt-bindings: timer: Add Milbeaut M10V timer description ARM: milbeaut: Add basic support for Milbeaut m10v SoC dt-bindings: Add documentation for Milbeaut SoCs dt-bindings: arm: Add SMP enable-method for Milbeaut dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram MAINTAINERS: Add entry for Bitmain SoC platform arm64: dts: bitmain: Add Sophon Egde board support arm64: dts: bitmain: Add BM1880 SoC support arm64: Add ARCH_BITMAIN platform dt-bindings: arm: Document Bitmain BM1880 SoC
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‎Documentation/devicetree/bindings/arm/bitmain.yaml

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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/bitmain.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bitmain platform device tree bindings
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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properties:
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compatible:
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items:
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- enum:
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- bitmain,sophon-edge
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- const: bitmain,bm1880
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...

‎Documentation/devicetree/bindings/arm/cpus.yaml

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@@ -228,6 +228,7 @@ patternProperties:
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- renesas,r9a06g032-smp
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- rockchip,rk3036-smp
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- rockchip,rk3066-smp
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- socionext,milbeaut-m10v-smp
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- ste,dbx500-smp
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cpu-release-addr:

‎Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml

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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/milbeaut.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Milbeaut platforms device tree bindings
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maintainers:
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- Taichi Sugaya <sugaya.taichi@socionext.com>
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- Takao Orito <orito.takao@socionext.com>
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- items:
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- enum:
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- socionext,milbeaut-m10v-evb
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- const: socionext,sc2000a
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...

‎Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt

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Milbeaut SRAM for smp bringup
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Milbeaut SoCs use a part of the sram for the bringup of the secondary cores.
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Once they get powered up in the bootloader, they stay at the specific part
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of the sram.
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Therefore the part needs to be added as the sub-node of mmio-sram.
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Required sub-node properties:
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- compatible : should be "socionext,milbeaut-smp-sram"
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Example:
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sram: sram@0 {
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compatible = "mmio-sram";
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reg = <0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x10000>;
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smp-sram@f100 {
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compatible = "socionext,milbeaut-smp-sram";
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reg = <0xf100 0x20>;
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};
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};

‎Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt

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Milbeaut SoCs Timer Controller
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Required properties:
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- compatible : should be "socionext,milbeaut-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : The interrupt of the first timer.
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- clocks: phandle to the input clk.
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Example:
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timer {
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compatible = "socionext,milbeaut-timer";
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reg = <0x1e000050 0x20>
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interrupts = <0 91 4>;
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clocks = <&clk 4>;
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};

‎MAINTAINERS

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F: arch/arm/boot/dts/aspeed-*
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N: aspeed
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ARM/BITMAIN ARCHITECTURE
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M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm64/boot/dts/bitmain/
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F: Documentation/devicetree/bindings/arm/bitmain.yaml
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ARM/CALXEDA HIGHBANK ARCHITECTURE
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M: Rob Herring <robh@kernel.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

‎arch/arm/Kconfig

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@@ -751,6 +751,8 @@ source "arch/arm/mach-mediatek/Kconfig"
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source "arch/arm/mach-meson/Kconfig"
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source "arch/arm/mach-milbeaut/Kconfig"
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source "arch/arm/mach-mmp/Kconfig"
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source "arch/arm/mach-moxart/Kconfig"

‎arch/arm/Makefile

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@@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
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machine-$(CONFIG_ARCH_MVEBU) += mvebu
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machine-$(CONFIG_ARCH_MXC) += imx
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machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
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machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut
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machine-$(CONFIG_ARCH_MXS) += mxs
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machine-$(CONFIG_ARCH_NETX) += netx
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machine-$(CONFIG_ARCH_NOMADIK) += nomadik

‎arch/arm/boot/dts/Makefile

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mt7623n-bananapi-bpi-r2.dtb \
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mt8127-moose.dtb \
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mt8135-evbp1.dtb
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dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
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dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
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dtb-$(CONFIG_ARCH_ASPEED) += \
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aspeed-ast2500-evb.dtb \

‎arch/arm/boot/dts/milbeaut-m10v-evb.dts

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// SPDX-License-Identifier: GPL-2.0
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/* Socionext Milbeaut M10V Evaluation Board */
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/dts-v1/;
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#include "milbeaut-m10v.dtsi"
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/ {
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model = "Socionext M10V EVB";
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compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a";
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aliases {
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serial0 = &uart1;
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};
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chosen {
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bootargs = "rootwait earlycon";
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stdout-path = "serial0:115200n8";
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};
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clocks {
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uclk40xi: uclk40xi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x80000000>;
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};
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};

‎arch/arm/boot/dts/milbeaut-m10v.dtsi

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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "socionext,sc2000a";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "socionext,milbeaut-m10v-smp";
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cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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};
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cpu@f02 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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};
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cpu@f03 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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};
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};
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timer { /* The Generic Timer */
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <40000000>;
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always-on;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&gic>;
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gic: interrupt-controller@1d000000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x1d001000 0x1000>,
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<0x1d002000 0x1000>; /* CPU I/f base and size */
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};
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timer@1e000050 { /* 32-bit Reload Timers */
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compatible = "socionext,milbeaut-timer";
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reg = <0x1e000050 0x20>;
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interrupts = <0 91 4>;
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};
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uart1: serial@1e700010 { /* PE4, PE5 */
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/* Enable this as ttyUSI0 */
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compatible = "socionext,milbeaut-usio-uart";
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reg = <0x1e700010 0x10>;
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interrupts = <0 141 0x4>, <0 149 0x4>;
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interrupt-names = "rx", "tx";
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};
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};
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sram@0 {
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compatible = "mmio-sram";
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reg = <0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x10000>;
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smp-sram@f100 {
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compatible = "socionext,milbeaut-smp-sram";
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reg = <0xf100 0x20>;
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};
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};
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};

‎arch/arm/configs/milbeaut_m10v_defconfig

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CONFIG_SYSVIPC=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_CGROUPS=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_EMBEDDED=y
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CONFIG_PERF_EVENTS=y
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CONFIG_ARCH_MILBEAUT=y
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CONFIG_ARCH_MILBEAUT_M10V=y
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CONFIG_ARM_THUMBEE=y
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# CONFIG_VDSO is not set
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# CONFIG_CACHE_L2X0 is not set
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CONFIG_ARM_ERRATA_430973=y
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CONFIG_ARM_ERRATA_720789=y
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CONFIG_ARM_ERRATA_754322=y
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CONFIG_ARM_ERRATA_754327=y
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CONFIG_ARM_ERRATA_764369=y
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CONFIG_ARM_ERRATA_775420=y
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CONFIG_ARM_ERRATA_798181=y
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CONFIG_SMP=y
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# CONFIG_SMP_ON_UP is not set
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# CONFIG_ARM_CPU_TOPOLOGY is not set
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CONFIG_HAVE_ARM_ARCH_TIMER=y
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CONFIG_NR_CPUS=16
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CONFIG_THUMB2_KERNEL=y
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# CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 is not set
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# CONFIG_ARM_PATCH_IDIV is not set
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CONFIG_HIGHMEM=y
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CONFIG_FORCE_MAX_ZONEORDER=12
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CONFIG_SECCOMP=y
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CONFIG_KEXEC=y
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CONFIG_EFI=y
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CONFIG_CPU_FREQ=y
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=m
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CONFIG_CPU_FREQ_GOV_USERSPACE=m
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CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
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CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_QORIQ_CPUFREQ=y
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CONFIG_CPU_IDLE=y
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CONFIG_ARM_CPUIDLE=y
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CONFIG_VFP=y
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CONFIG_NEON=y
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CONFIG_KERNEL_MODE_NEON=y
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CONFIG_EFI_VARS=m
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CONFIG_EFI_CAPSULE_LOADER=m
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CONFIG_ARM_CRYPTO=y
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CONFIG_CRYPTO_SHA1_ARM_NEON=m
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CONFIG_CRYPTO_SHA1_ARM_CE=m
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CONFIG_CRYPTO_SHA2_ARM_CE=m
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CONFIG_CRYPTO_SHA512_ARM=m
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CONFIG_CRYPTO_AES_ARM=m
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CONFIG_CRYPTO_AES_ARM_BS=m
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CONFIG_CRYPTO_AES_ARM_CE=m
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CONFIG_CRYPTO_GHASH_ARM_CE=m
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CONFIG_CRYPTO_CRC32_ARM_CE=m
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CONFIG_CRYPTO_CHACHA20_NEON=m
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_CMDLINE_PARTITION=y
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CONFIG_CMA=y
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_DMA_CMA=y
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CONFIG_CMA_SIZE_MBYTES=64
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CONFIG_OF_OVERLAY=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_SIZE=65536
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CONFIG_SRAM=y
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CONFIG_INPUT_FF_MEMLESS=m
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CONFIG_INPUT_MATRIXKMAP=y
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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CONFIG_SERIO_LIBPS2=y
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CONFIG_VT_HW_CONSOLE_BINDING=y
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CONFIG_SERIAL_DEV_BUS=y
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# CONFIG_HW_RANDOM is not set
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_GENERIC_PLATFORM=y
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# CONFIG_HWMON is not set
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CONFIG_MEDIA_SUPPORT=m
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CONFIG_MEDIA_CAMERA_SUPPORT=y
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CONFIG_MEDIA_CONTROLLER=y
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# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
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# CONFIG_HID is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_SYNC_FILE=y
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# CONFIG_VIRTIO_MENU is not set
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# CONFIG_IOMMU_SUPPORT is not set
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CONFIG_SOC_BRCMSTB=y
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CONFIG_MEMORY=y
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# CONFIG_ARM_PMU is not set
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CONFIG_EXT4_FS=y
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CONFIG_AUTOFS4_FS=y
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CONFIG_MSDOS_FS=y
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CONFIG_VFAT_FS=y
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CONFIG_NTFS_FS=y
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CONFIG_TMPFS=y
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CONFIG_TMPFS_POSIX_ACL=y
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CONFIG_CONFIGFS_FS=y
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# CONFIG_MISC_FILESYSTEMS is not set
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ISO8859_1=y
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CONFIG_NLS_UTF8=y
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CONFIG_KEYS=y
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CONFIG_CRYPTO_MANAGER=y
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# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
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CONFIG_CRYPTO_SEQIV=m
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# CONFIG_CRYPTO_ECHAINIV is not set
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CONFIG_CRYPTO_AES=y
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# CONFIG_CRYPTO_HW is not set
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CONFIG_CRC_CCITT=m
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CONFIG_CRC_ITU_T=m
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CONFIG_PRINTK_TIME=y
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CONFIG_MAGIC_SYSRQ=y

‎arch/arm/configs/multi_v7_defconfig

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CONFIG_ARCH_KEYSTONE=y
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CONFIG_ARCH_MEDIATEK=y
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CONFIG_ARCH_MESON=y
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CONFIG_ARCH_MILBEAUT=y
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CONFIG_ARCH_MILBEAUT_M10V=y
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CONFIG_ARCH_MVEBU=y
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CONFIG_MACH_ARMADA_370=y
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CONFIG_MACH_ARMADA_375=y

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