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Merge tag 'drm-fixes-for-v4.16-rc5' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "There are a small set of sun4i and i915 fixes, and many more amdgpu fixes: sun4i: - divide by zero fix - clock and LVDS fixes i915: - fix for perf - race fix amdgpu: - a bit more than we are normally comfortable with at this point, however it does fix a lot of display issues with the new DC code which result in black screens in various configurations along with some run of the mill gpu configuration fixes. I'm happy enough that the fixes are limited to the DC code and should fix a bunch of issues on the new raven ridge APUs that we are seeing shipped now" * tag 'drm-fixes-for-v4.16-rc5' of git://people.freedesktop.org/~airlied/linux: (42 commits) drm/amd/display: validate plane format on primary plane drm/amdgpu:Always save uvd vcpu_bo in VM Mode drm/amdgpu:Correct max uvd handles drm/amd/display: early return if not in vga mode in disable_vga drm/amd/display: Fix takover from VGA mode drm/amd/display: Fix memleaks when atomic check fails. drm/amd/display: Return success when enabling interrupt drm/amd/display: Use crtc enable/disable_vblank hooks drm/amd/display: update infoframe after dig fe is turned on drm/amd/display: fix boot-up on vega10 drm/amd/display: fix cursor related Pstate hang drm/amd/display: Set irq state only on existing crtcs drm/amd/display: Fixed non-native modes not lighting up drm/amd/display: Call update_stream_signal directly from amdgpu_dm drm/amd/display: Make create_stream_for_sink more consistent drm/amd/display: Don't block dual-link DVI modes drm/amd/display: Don't allow dual-link DVI on all ASICs. drm/amd/display: Pass signal directly to enable_tmds_output drm/amd/display: Remove unnecessary fail labels in create_stream_for_sink drm/amd/display: Move MAX_TMDS_CLOCK define to header ...
2 parents dfbab3f + b0655d6 commit 65307f2

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41 files changed

+464
-366
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -540,6 +540,9 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
540540
size_t size;
541541
u32 retry = 3;
542542

543+
if (amdgpu_acpi_pcie_notify_device_ready(adev))
544+
return -EINVAL;
545+
543546
/* Get the device handle */
544547
handle = ACPI_HANDLE(&adev->pdev->dev);
545548
if (!handle)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -481,7 +481,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
481481
result = 0;
482482

483483
if (*pos < 12) {
484-
early[0] = amdgpu_ring_get_rptr(ring);
484+
early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
485485
early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
486486
early[2] = ring->wptr & ring->buf_mask;
487487
for (i = *pos / 4; i < 3 && size; i++) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -299,12 +299,15 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
299299

300300
cancel_delayed_work_sync(&adev->uvd.idle_work);
301301

302-
for (i = 0; i < adev->uvd.max_handles; ++i)
303-
if (atomic_read(&adev->uvd.handles[i]))
304-
break;
302+
/* only valid for physical mode */
303+
if (adev->asic_type < CHIP_POLARIS10) {
304+
for (i = 0; i < adev->uvd.max_handles; ++i)
305+
if (atomic_read(&adev->uvd.handles[i]))
306+
break;
305307

306-
if (i == AMDGPU_MAX_UVD_HANDLES)
307-
return 0;
308+
if (i == adev->uvd.max_handles)
309+
return 0;
310+
}
308311

309312
size = amdgpu_bo_size(adev->uvd.vcpu_bo);
310313
ptr = adev->uvd.cpu_addr;

‎drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3093,7 +3093,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
30933093
tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
30943094
WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
30953095
schedule_work(&adev->hotplug_work);
3096-
DRM_INFO("IH: HPD%d\n", hpd + 1);
3096+
DRM_DEBUG("IH: HPD%d\n", hpd + 1);
30973097
}
30983098

30993099
return 0;

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

Lines changed: 2 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -4384,34 +4384,8 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
43844384
case CHIP_KAVERI:
43854385
adev->gfx.config.max_shader_engines = 1;
43864386
adev->gfx.config.max_tile_pipes = 4;
4387-
if ((adev->pdev->device == 0x1304) ||
4388-
(adev->pdev->device == 0x1305) ||
4389-
(adev->pdev->device == 0x130C) ||
4390-
(adev->pdev->device == 0x130F) ||
4391-
(adev->pdev->device == 0x1310) ||
4392-
(adev->pdev->device == 0x1311) ||
4393-
(adev->pdev->device == 0x131C)) {
4394-
adev->gfx.config.max_cu_per_sh = 8;
4395-
adev->gfx.config.max_backends_per_se = 2;
4396-
} else if ((adev->pdev->device == 0x1309) ||
4397-
(adev->pdev->device == 0x130A) ||
4398-
(adev->pdev->device == 0x130D) ||
4399-
(adev->pdev->device == 0x1313) ||
4400-
(adev->pdev->device == 0x131D)) {
4401-
adev->gfx.config.max_cu_per_sh = 6;
4402-
adev->gfx.config.max_backends_per_se = 2;
4403-
} else if ((adev->pdev->device == 0x1306) ||
4404-
(adev->pdev->device == 0x1307) ||
4405-
(adev->pdev->device == 0x130B) ||
4406-
(adev->pdev->device == 0x130E) ||
4407-
(adev->pdev->device == 0x1315) ||
4408-
(adev->pdev->device == 0x131B)) {
4409-
adev->gfx.config.max_cu_per_sh = 4;
4410-
adev->gfx.config.max_backends_per_se = 1;
4411-
} else {
4412-
adev->gfx.config.max_cu_per_sh = 3;
4413-
adev->gfx.config.max_backends_per_se = 1;
4414-
}
4387+
adev->gfx.config.max_cu_per_sh = 8;
4388+
adev->gfx.config.max_backends_per_se = 2;
44154389
adev->gfx.config.max_sh_per_se = 1;
44164390
adev->gfx.config.max_texture_channel_caches = 4;
44174391
adev->gfx.config.max_gprs = 256;

‎drivers/gpu/drm/amd/amdgpu/si.c

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
#include "amdgpu_uvd.h"
3232
#include "amdgpu_vce.h"
3333
#include "atom.h"
34+
#include "amd_pcie.h"
3435
#include "amdgpu_powerplay.h"
3536
#include "sid.h"
3637
#include "si_ih.h"
@@ -1461,8 +1462,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
14611462
{
14621463
struct pci_dev *root = adev->pdev->bus->self;
14631464
int bridge_pos, gpu_pos;
1464-
u32 speed_cntl, mask, current_data_rate;
1465-
int ret, i;
1465+
u32 speed_cntl, current_data_rate;
1466+
int i;
14661467
u16 tmp16;
14671468

14681469
if (pci_is_root_bus(adev->pdev->bus))
@@ -1474,23 +1475,20 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
14741475
if (adev->flags & AMD_IS_APU)
14751476
return;
14761477

1477-
ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1478-
if (ret != 0)
1479-
return;
1480-
1481-
if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1478+
if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1479+
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
14821480
return;
14831481

14841482
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
14851483
current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
14861484
LC_CURRENT_DATA_RATE_SHIFT;
1487-
if (mask & DRM_PCIE_SPEED_80) {
1485+
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
14881486
if (current_data_rate == 2) {
14891487
DRM_INFO("PCIE gen 3 link speeds already enabled\n");
14901488
return;
14911489
}
14921490
DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1493-
} else if (mask & DRM_PCIE_SPEED_50) {
1491+
} else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
14941492
if (current_data_rate == 1) {
14951493
DRM_INFO("PCIE gen 2 link speeds already enabled\n");
14961494
return;
@@ -1506,7 +1504,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
15061504
if (!gpu_pos)
15071505
return;
15081506

1509-
if (mask & DRM_PCIE_SPEED_80) {
1507+
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
15101508
if (current_data_rate != 2) {
15111509
u16 bridge_cfg, gpu_cfg;
15121510
u16 bridge_cfg2, gpu_cfg2;
@@ -1589,9 +1587,9 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
15891587

15901588
pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
15911589
tmp16 &= ~0xf;
1592-
if (mask & DRM_PCIE_SPEED_80)
1590+
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
15931591
tmp16 |= 3;
1594-
else if (mask & DRM_PCIE_SPEED_50)
1592+
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
15951593
tmp16 |= 2;
15961594
else
15971595
tmp16 |= 1;

‎drivers/gpu/drm/amd/amdgpu/si_dpm.c

Lines changed: 13 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#include "amdgpu_pm.h"
2727
#include "amdgpu_dpm.h"
2828
#include "amdgpu_atombios.h"
29+
#include "amd_pcie.h"
2930
#include "sid.h"
3031
#include "r600_dpm.h"
3132
#include "si_dpm.h"
@@ -3331,29 +3332,6 @@ static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
33313332
}
33323333
}
33333334

3334-
static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3335-
u32 sys_mask,
3336-
enum amdgpu_pcie_gen asic_gen,
3337-
enum amdgpu_pcie_gen default_gen)
3338-
{
3339-
switch (asic_gen) {
3340-
case AMDGPU_PCIE_GEN1:
3341-
return AMDGPU_PCIE_GEN1;
3342-
case AMDGPU_PCIE_GEN2:
3343-
return AMDGPU_PCIE_GEN2;
3344-
case AMDGPU_PCIE_GEN3:
3345-
return AMDGPU_PCIE_GEN3;
3346-
default:
3347-
if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3348-
return AMDGPU_PCIE_GEN3;
3349-
else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3350-
return AMDGPU_PCIE_GEN2;
3351-
else
3352-
return AMDGPU_PCIE_GEN1;
3353-
}
3354-
return AMDGPU_PCIE_GEN1;
3355-
}
3356-
33573335
static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
33583336
u32 *p, u32 *u)
33593337
{
@@ -5028,10 +5006,11 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
50285006
table->ACPIState.levels[0].vddc.index,
50295007
&table->ACPIState.levels[0].std_vddc);
50305008
}
5031-
table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5032-
si_pi->sys_pcie_mask,
5033-
si_pi->boot_pcie_gen,
5034-
AMDGPU_PCIE_GEN1);
5009+
table->ACPIState.levels[0].gen2PCIE =
5010+
(u8)amdgpu_get_pcie_gen_support(adev,
5011+
si_pi->sys_pcie_mask,
5012+
si_pi->boot_pcie_gen,
5013+
AMDGPU_PCIE_GEN1);
50355014

50365015
if (si_pi->vddc_phase_shed_control)
50375016
si_populate_phase_shedding_value(adev,
@@ -7168,10 +7147,10 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
71687147
pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
71697148
pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
71707149
pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7171-
pl->pcie_gen = r600_get_pcie_gen_support(adev,
7172-
si_pi->sys_pcie_mask,
7173-
si_pi->boot_pcie_gen,
7174-
clock_info->si.ucPCIEGen);
7150+
pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
7151+
si_pi->sys_pcie_mask,
7152+
si_pi->boot_pcie_gen,
7153+
clock_info->si.ucPCIEGen);
71757154

71767155
/* patch up vddc if necessary */
71777156
ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
@@ -7326,7 +7305,6 @@ static int si_dpm_init(struct amdgpu_device *adev)
73267305
struct si_power_info *si_pi;
73277306
struct atom_clock_dividers dividers;
73287307
int ret;
7329-
u32 mask;
73307308

73317309
si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
73327310
if (si_pi == NULL)
@@ -7336,11 +7314,9 @@ static int si_dpm_init(struct amdgpu_device *adev)
73367314
eg_pi = &ni_pi->eg;
73377315
pi = &eg_pi->rv7xx;
73387316

7339-
ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7340-
if (ret)
7341-
si_pi->sys_pcie_mask = 0;
7342-
else
7343-
si_pi->sys_pcie_mask = mask;
7317+
si_pi->sys_pcie_mask =
7318+
(adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
7319+
CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
73447320
si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
73457321
si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
73467322

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