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torvaldstorvalds
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle: "Another round of fixes: - CM: Fix mips_cm_max_vp_width for non-MT kernels on MT systems - CPS: Avoid BUG() when offlining pre-r6 CPUs - DEC: Avoid gas warnings due to suspicious instruction scheduling by manually expanding assembler macros. - FTLB: Fix configuration by moving confiuguratoin after probing - FTLB: clear execution hazard after changing FTLB enable - Highmem: Fix detection of unsupported highmem with cache aliases - I6400: Don't touch FTLBP chicken bits - microMIPS: Fix BUILD_ROLLBACK_PROLOGUE - Malta: Fix IOCU disable switch read for MIPS64 - Octeon: Fix probing of devices attached to GPIO lines - uprobes: Misc small fixes" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: CM: Fix mips_cm_max_vp_width for non-MT kernels on MT systems MIPS: Fix detection of unsupported highmem with cache aliases MIPS: Malta: Fix IOCU disable switch read for MIPS64 MIPS: Fix BUILD_ROLLBACK_PROLOGUE for microMIPS MIPS: clear execution hazard after changing FTLB enable MIPS: Configure FTLB after probing TLB sizes from config4 MIPS: Stop setting I6400 FTLBP MIPS: DEC: Avoid la pseudo-instruction in delay slots MIPS: Octeon: mark GPIO controller node not populated after IRQ init. MIPS: uprobes: fix use of uninitialised variable MIPS: uprobes: remove incorrect set_orig_insn MIPS: fix uretprobe implementation MIPS: smp-cps: Avoid BUG() when offlining pre-r6 CPUs
2 parents 0c7fc30 + 6605d15 commit 66188fb

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lines changed

12 files changed

+101
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lines changed

‎arch/mips/cavium-octeon/octeon-irq.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1619,6 +1619,12 @@ static int __init octeon_irq_init_gpio(
16191619
return -ENOMEM;
16201620
}
16211621

1622+
/*
1623+
* Clear the OF_POPULATED flag that was set by of_irq_init()
1624+
* so that all GPIO devices will be probed.
1625+
*/
1626+
of_node_clear_flag(gpio_node, OF_POPULATED);
1627+
16221628
return 0;
16231629
}
16241630
/*

‎arch/mips/dec/int-handler.S

Lines changed: 38 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,25 @@
146146
/*
147147
* Find irq with highest priority
148148
*/
149-
PTR_LA t1,cpu_mask_nr_tbl
149+
# open coded PTR_LA t1, cpu_mask_nr_tbl
150+
#if (_MIPS_SZPTR == 32)
151+
# open coded la t1, cpu_mask_nr_tbl
152+
lui t1, %hi(cpu_mask_nr_tbl)
153+
addiu t1, %lo(cpu_mask_nr_tbl)
154+
155+
#endif
156+
#if (_MIPS_SZPTR == 64)
157+
# open coded dla t1, cpu_mask_nr_tbl
158+
.set push
159+
.set noat
160+
lui t1, %highest(cpu_mask_nr_tbl)
161+
lui AT, %hi(cpu_mask_nr_tbl)
162+
daddiu t1, t1, %higher(cpu_mask_nr_tbl)
163+
daddiu AT, AT, %lo(cpu_mask_nr_tbl)
164+
dsll t1, 32
165+
daddu t1, t1, AT
166+
.set pop
167+
#endif
150168
1: lw t2,(t1)
151169
nop
152170
and t2,t0
@@ -195,7 +213,25 @@
195213
/*
196214
* Find irq with highest priority
197215
*/
198-
PTR_LA t1,asic_mask_nr_tbl
216+
# open coded PTR_LA t1,asic_mask_nr_tbl
217+
#if (_MIPS_SZPTR == 32)
218+
# open coded la t1, asic_mask_nr_tbl
219+
lui t1, %hi(asic_mask_nr_tbl)
220+
addiu t1, %lo(asic_mask_nr_tbl)
221+
222+
#endif
223+
#if (_MIPS_SZPTR == 64)
224+
# open coded dla t1, asic_mask_nr_tbl
225+
.set push
226+
.set noat
227+
lui t1, %highest(asic_mask_nr_tbl)
228+
lui AT, %hi(asic_mask_nr_tbl)
229+
daddiu t1, t1, %higher(asic_mask_nr_tbl)
230+
daddiu AT, AT, %lo(asic_mask_nr_tbl)
231+
dsll t1, 32
232+
daddu t1, t1, AT
233+
.set pop
234+
#endif
199235
2: lw t2,(t1)
200236
nop
201237
and t2,t0

‎arch/mips/include/asm/mips-cm.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -458,10 +458,21 @@ static inline int mips_cm_revision(void)
458458
static inline unsigned int mips_cm_max_vp_width(void)
459459
{
460460
extern int smp_num_siblings;
461+
uint32_t cfg;
461462

462463
if (mips_cm_revision() >= CM_REV_CM3)
463464
return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;
464465

466+
if (mips_cm_present()) {
467+
/*
468+
* We presume that all cores in the system will have the same
469+
* number of VP(E)s, and if that ever changes then this will
470+
* need revisiting.
471+
*/
472+
cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
473+
return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
474+
}
475+
465476
if (IS_ENABLED(CONFIG_SMP))
466477
return smp_num_siblings;
467478

‎arch/mips/include/asm/mipsregs.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -660,8 +660,6 @@
660660

661661
#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
662662
#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
663-
/* FTLB probability bits for R6 */
664-
#define MIPS_CONF7_FTLBP_SHIFT (18)
665663

666664
/* WatchLo* register definitions */
667665
#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)

‎arch/mips/include/asm/uprobes.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ struct arch_uprobe {
3636
unsigned long resume_epc;
3737
u32 insn[2];
3838
u32 ixol[2];
39-
union mips_instruction orig_inst[MAX_UINSN_BYTES / 4];
4039
};
4140

4241
struct arch_uprobe_task {

‎arch/mips/kernel/cpu-probe.c

Lines changed: 30 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -352,7 +352,12 @@ __setup("nohtw", htw_disable);
352352
static int mips_ftlb_disabled;
353353
static int mips_has_ftlb_configured;
354354

355-
static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
355+
enum ftlb_flags {
356+
FTLB_EN = 1 << 0,
357+
FTLB_SET_PROB = 1 << 1,
358+
};
359+
360+
static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
356361

357362
static int __init ftlb_disable(char *s)
358363
{
@@ -371,8 +376,6 @@ static int __init ftlb_disable(char *s)
371376
return 1;
372377
}
373378

374-
back_to_back_c0_hazard();
375-
376379
config4 = read_c0_config4();
377380

378381
/* Check that FTLB has been disabled */
@@ -531,7 +534,7 @@ static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
531534
return 3;
532535
}
533536

534-
static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
537+
static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
535538
{
536539
unsigned int config;
537540

@@ -542,33 +545,33 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
542545
case CPU_P6600:
543546
/* proAptiv & related cores use Config6 to enable the FTLB */
544547
config = read_c0_config6();
545-
/* Clear the old probability value */
546-
config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
547-
if (enable)
548-
/* Enable FTLB */
549-
write_c0_config6(config |
550-
(calculate_ftlb_probability(c)
551-
<< MIPS_CONF6_FTLBP_SHIFT)
552-
| MIPS_CONF6_FTLBEN);
548+
549+
if (flags & FTLB_EN)
550+
config |= MIPS_CONF6_FTLBEN;
553551
else
554-
/* Disable FTLB */
555-
write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
552+
config &= ~MIPS_CONF6_FTLBEN;
553+
554+
if (flags & FTLB_SET_PROB) {
555+
config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
556+
config |= calculate_ftlb_probability(c)
557+
<< MIPS_CONF6_FTLBP_SHIFT;
558+
}
559+
560+
write_c0_config6(config);
561+
back_to_back_c0_hazard();
556562
break;
557563
case CPU_I6400:
558-
/* I6400 & related cores use Config7 to configure FTLB */
559-
config = read_c0_config7();
560-
/* Clear the old probability value */
561-
config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
562-
write_c0_config7(config | (calculate_ftlb_probability(c)
563-
<< MIPS_CONF7_FTLBP_SHIFT));
564-
break;
564+
/* There's no way to disable the FTLB */
565+
if (!(flags & FTLB_EN))
566+
return 1;
567+
return 0;
565568
case CPU_LOONGSON3:
566569
/* Flush ITLB, DTLB, VTLB and FTLB */
567570
write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
568571
LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
569572
/* Loongson-3 cores use Config6 to enable the FTLB */
570573
config = read_c0_config6();
571-
if (enable)
574+
if (flags & FTLB_EN)
572575
/* Enable FTLB */
573576
write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
574577
else
@@ -788,6 +791,7 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
788791
PAGE_SIZE, config4);
789792
/* Switch FTLB off */
790793
set_ftlb_enable(c, 0);
794+
mips_ftlb_disabled = 1;
791795
break;
792796
}
793797
c->tlbsizeftlbsets = 1 <<
@@ -852,7 +856,7 @@ static void decode_configs(struct cpuinfo_mips *c)
852856
c->scache.flags = MIPS_CACHE_NOT_PRESENT;
853857

854858
/* Enable FTLB if present and not disabled */
855-
set_ftlb_enable(c, !mips_ftlb_disabled);
859+
set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
856860

857861
ok = decode_config0(c); /* Read Config registers. */
858862
BUG_ON(!ok); /* Arch spec violation! */
@@ -902,6 +906,9 @@ static void decode_configs(struct cpuinfo_mips *c)
902906
}
903907
}
904908

909+
/* configure the FTLB write probability */
910+
set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
911+
905912
mips_probe_watch_registers(c);
906913

907914
#ifndef CONFIG_MIPS_CPS

‎arch/mips/kernel/genex.S

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -142,9 +142,8 @@ LEAF(__r4k_wait)
142142
PTR_LA k1, __r4k_wait
143143
ori k0, 0x1f /* 32 byte rollback region */
144144
xori k0, 0x1f
145-
bne k0, k1, 9f
145+
bne k0, k1, \handler
146146
MTC0 k0, CP0_EPC
147-
9:
148147
.set pop
149148
.endm
150149

‎arch/mips/kernel/setup.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -764,7 +764,6 @@ static void __init arch_mem_init(char **cmdline_p)
764764
device_tree_init();
765765
sparse_init();
766766
plat_swiotlb_setup();
767-
paging_init();
768767

769768
dma_contiguous_reserve(PFN_PHYS(max_low_pfn));
770769
/* Tell bootmem about cma reserved memblock section */
@@ -877,6 +876,7 @@ void __init setup_arch(char **cmdline_p)
877876
prefill_possible_map();
878877

879878
cpu_cache_init();
879+
paging_init();
880880
}
881881

882882
unsigned long kernelsp[NR_CPUS];

‎arch/mips/kernel/smp-cps.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -513,7 +513,7 @@ static void cps_cpu_die(unsigned int cpu)
513513
* in which case the CPC will refuse to power down the core.
514514
*/
515515
do {
516-
mips_cm_lock_other(core, vpe_id);
516+
mips_cm_lock_other(core, 0);
517517
mips_cpc_lock_other(core);
518518
stat = read_cpc_co_stat_conf();
519519
stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;

‎arch/mips/kernel/uprobes.c

Lines changed: 3 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,6 @@ bool is_trap_insn(uprobe_opcode_t *insn)
157157
int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs)
158158
{
159159
struct uprobe_task *utask = current->utask;
160-
union mips_instruction insn;
161160

162161
/*
163162
* Now find the EPC where to resume after the breakpoint has been
@@ -168,10 +167,10 @@ int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs)
168167
unsigned long epc;
169168

170169
epc = regs->cp0_epc;
171-
__compute_return_epc_for_insn(regs, insn);
170+
__compute_return_epc_for_insn(regs,
171+
(union mips_instruction) aup->insn[0]);
172172
aup->resume_epc = regs->cp0_epc;
173173
}
174-
175174
utask->autask.saved_trap_nr = current->thread.trap_nr;
176175
current->thread.trap_nr = UPROBE_TRAP_NR;
177176
regs->cp0_epc = current->utask->xol_vaddr;
@@ -257,7 +256,7 @@ unsigned long arch_uretprobe_hijack_return_addr(
257256
ra = regs->regs[31];
258257

259258
/* Replace the return address with the trampoline address */
260-
regs->regs[31] = ra;
259+
regs->regs[31] = trampoline_vaddr;
261260

262261
return ra;
263262
}
@@ -280,24 +279,6 @@ int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
280279
return uprobe_write_opcode(mm, vaddr, UPROBE_SWBP_INSN);
281280
}
282281

283-
/**
284-
* set_orig_insn - Restore the original instruction.
285-
* @mm: the probed process address space.
286-
* @auprobe: arch specific probepoint information.
287-
* @vaddr: the virtual address to insert the opcode.
288-
*
289-
* For mm @mm, restore the original opcode (opcode) at @vaddr.
290-
* Return 0 (success) or a negative errno.
291-
*
292-
* This overrides the weak version in kernel/events/uprobes.c.
293-
*/
294-
int set_orig_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
295-
unsigned long vaddr)
296-
{
297-
return uprobe_write_opcode(mm, vaddr,
298-
*(uprobe_opcode_t *)&auprobe->orig_inst[0].word);
299-
}
300-
301282
void __weak arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
302283
void *src, unsigned long len)
303284
{

‎arch/mips/mm/init.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -440,6 +440,9 @@ static inline void mem_init_free_highmem(void)
440440
#ifdef CONFIG_HIGHMEM
441441
unsigned long tmp;
442442

443+
if (cpu_has_dc_aliases)
444+
return;
445+
443446
for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
444447
struct page *page = pfn_to_page(tmp);
445448

‎arch/mips/mti-malta/malta-setup.c

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,9 @@
3939
#include <linux/console.h>
4040
#endif
4141

42+
#define ROCIT_CONFIG_GEN0 0x1f403000
43+
#define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7)
44+
4245
extern void malta_be_init(void);
4346
extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
4447

@@ -107,6 +110,8 @@ static void __init fd_activate(void)
107110
static int __init plat_enable_iocoherency(void)
108111
{
109112
int supported = 0;
113+
u32 cfg;
114+
110115
if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
111116
if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
112117
BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
@@ -129,7 +134,8 @@ static int __init plat_enable_iocoherency(void)
129134
} else if (mips_cm_numiocu() != 0) {
130135
/* Nothing special needs to be done to enable coherency */
131136
pr_info("CMP IOCU detected\n");
132-
if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
137+
cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
138+
if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
133139
pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
134140
return 0;
135141
}

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