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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq core updates from Thomas Gleixner: "A rather large update for the interrupt core code and the irq chip drivers: - Add a new bitmap matrix allocator and supporting changes, which is used to replace the x86 vector allocator which comes with separate pull request. This allows to replace the convoluted nested loop allocation function in x86 with a facility which supports the recently added property of managed interrupts proper and allows to switch to a best effort vector reservation scheme, which addresses problems with vector exhaustion. - A large update to the ARM GIC-V3-ITS driver adding support for range selectors. - New interrupt controllers: - Meson and Meson8 GPIO - BCM7271 L2 - Socionext EXIU If you expected that this will stop at some point, I have to disappoint you. There are new ones posted already. Sigh! - STM32 interrupt controller support for new platforms. - A pile of fixes, cleanups and updates to the MIPS GIC driver - The usual small fixes, cleanups and updates all over the place. Most visible one is to move the irq chip drivers Kconfig switches into a separate Kconfig menu" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (70 commits) genirq: Fix type of shifting literal 1 in __setup_irq() irqdomain: Drop pointless NULL check in virq_debug_show_one genirq/proc: Return proper error code when irq_set_affinity() fails irq/work: Use llist_for_each_entry_safe irqchip: mips-gic: Print warning if inherited GIC base is used irqchip/mips-gic: Add pr_fmt and reword pr_* messages irqchip/stm32: Move the wakeup on interrupt mask irqchip/stm32: Fix initial values irqchip/stm32: Add stm32h7 support dt-bindings/interrupt-controllers: Add compatible string for stm32h7 irqchip/stm32: Add multi-bank management irqchip/stm32: Select GENERIC_IRQ_CHIP irqchip/exiu: Add support for Socionext Synquacer EXIU controller dt-bindings: Add description of Socionext EXIU interrupt controller irqchip/gic-v3-its: Fix VPE activate callback return value irqchip: mips-gic: Make IPI bitmaps static irqchip: mips-gic: Share register writes in gic_set_type() irqchip: mips-gic: Remove gic_vpes variable irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs irqchip: mips-gic: Configure EIC when CPUs come online ...
2 parents 43ff2f4 + ffc661c commit 670310d

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‎Documentation/admin-guide/kernel-parameters.txt

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1716,6 +1716,13 @@
17161716
irqaffinity= [SMP] Set the default irq affinity mask
17171717
The argument is a cpu list, as described above.
17181718

1719+
irqchip.gicv2_force_probe=
1720+
[ARM, ARM64]
1721+
Format: <bool>
1722+
Force the kernel to look for the second 4kB page
1723+
of a GICv2 controller even if the memory range
1724+
exposed by the device tree is too small.
1725+
17191726
irqfixup [HW]
17201727
When an interrupt is not handled search all handlers
17211728
for it. Intended to get systems with badly broken

‎Documentation/arm64/silicon-errata.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ stable kernels.
7070
| | | | |
7171
| Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |
7272
| Hisilicon | Hip0{6,7} | #161010701 | N/A |
73+
| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
7374
| | | | |
7475
| Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
7576
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |

‎Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
Amlogic meson GPIO interrupt controller
2+
3+
Meson SoCs contains an interrupt controller which is able to watch the SoC
4+
pads and generate an interrupt on edge or level. The controller is essentially
5+
a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
6+
or level and polarity. It does not expose all 256 mux inputs because the
7+
documentation shows that the upper part is not mapped to any pad. The actual
8+
number of interrupt exposed depends on the SoC.
9+
10+
Required properties:
11+
12+
- compatible : must have "amlogic,meson8-gpio-intc” and either
13+
“amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or
14+
“amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
15+
“amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or
16+
“amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)
17+
- interrupt-parent : a phandle to the GIC the interrupts are routed to.
18+
Usually this is provided at the root level of the device tree as it is
19+
common to most of the SoC.
20+
- reg : Specifies base physical address and size of the registers.
21+
- interrupt-controller : Identifies the node as an interrupt controller.
22+
- #interrupt-cells : Specifies the number of cells needed to encode an
23+
interrupt source. The value must be 2.
24+
- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
25+
are the hwirqs used on the parent interrupt controller.
26+
27+
Example:
28+
29+
gpio_interrupt: interrupt-controller@9880 {
30+
compatible = "amlogic,meson-gxbb-gpio-intc",
31+
"amlogic,meson-gpio-intc";
32+
reg = <0x0 0x9880 0x0 0x10>;
33+
interrupt-controller;
34+
#interrupt-cells = <2>;
35+
meson,channel-interrupts = <64 65 66 67 68 69 70 71>;
36+
};

‎Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,10 @@ These nodes must have the following properties:
7575
- reg: Specifies the base physical address and size of the ITS
7676
registers.
7777

78+
Optional:
79+
- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated
80+
address and size of the pre-ITS window.
81+
7882
The main GIC node must contain the appropriate #address-cells,
7983
#size-cells and ranges properties for the reg property of all ITS
8084
nodes.

‎Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller
22

33
Required properties:
44

5-
- compatible: should be "brcm,l2-intc"
5+
- compatible: should be "brcm,l2-intc" for latched interrupt controllers
6+
should be "brcm,bcm7271-l2-intc" for level interrupt controllers
67
- reg: specifies the base physical address and size of the registers
78
- interrupt-controller: identifies the node as an interrupt controller
89
- #interrupt-cells: specifies the number of cells needed to encode an

‎Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,9 @@ Required properties:
1313
- "renesas,irqc-r8a7793" (R-Car M2-N)
1414
- "renesas,irqc-r8a7794" (R-Car E2)
1515
- "renesas,intc-ex-r8a7795" (R-Car H3)
16+
- "renesas,intc-ex-r8a7796" (R-Car M3-W)
17+
- "renesas,intc-ex-r8a77970" (R-Car V3M)
18+
- "renesas,intc-ex-r8a77995" (R-Car D3)
1619
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
1720
interrupts.txt in this directory
1821
- clocks: Must contain a reference to the functional clock.

‎Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
Socionext SynQuacer External Interrupt Unit (EXIU)
2+
3+
The Socionext Synquacer SoC has an external interrupt unit (EXIU)
4+
that forwards a block of 32 configurable input lines to 32 adjacent
5+
level-high type GICv3 SPIs.
6+
7+
Required properties:
8+
9+
- compatible : Should be "socionext,synquacer-exiu".
10+
- reg : Specifies base physical address and size of the
11+
control registers.
12+
- interrupt-controller : Identifies the node as an interrupt controller.
13+
- #interrupt-cells : Specifies the number of cells needed to encode an
14+
interrupt source. The value must be 3.
15+
- interrupt-parent : phandle of the GIC these interrupts are routed to.
16+
- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
17+
ones the EXIU forwards its interrups to.
18+
19+
Notes:
20+
21+
- Only SPIs can use the EXIU as an interrupt parent.
22+
23+
Example:
24+
25+
exiu: interrupt-controller@510c0000 {
26+
compatible = "socionext,synquacer-exiu";
27+
reg = <0x0 0x510c0000 0x0 0x20>;
28+
interrupt-controller;
29+
interrupt-parent = <&gic>;
30+
#interrupt-cells = <3>;
31+
socionext,spi-base = <112>;
32+
};

‎Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,9 @@ STM32 External Interrupt Controller
22

33
Required properties:
44

5-
- compatible: Should be "st,stm32-exti"
5+
- compatible: Should be:
6+
"st,stm32-exti"
7+
"st,stm32h7-exti"
68
- reg: Specifies base physical address and size of the registers
79
- interrupt-controller: Indentifies the node as an interrupt controller
810
- #interrupt-cells: Specifies the number of cells to encode an interrupt

‎arch/arm/include/asm/arch_gicv3.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -196,6 +196,11 @@ static inline void gic_write_ctlr(u32 val)
196196
isb();
197197
}
198198

199+
static inline u32 gic_read_ctlr(void)
200+
{
201+
return read_sysreg(ICC_CTLR);
202+
}
203+
199204
static inline void gic_write_grpen1(u32 val)
200205
{
201206
write_sysreg(val, ICC_IGRPEN1);

‎arch/arm64/Kconfig

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -556,6 +556,25 @@ config QCOM_QDF2400_ERRATUM_0065
556556

557557
If unsure, say Y.
558558

559+
560+
config SOCIONEXT_SYNQUACER_PREITS
561+
bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
562+
default y
563+
help
564+
Socionext Synquacer SoCs implement a separate h/w block to generate
565+
MSI doorbell writes with non-zero values for the device ID.
566+
567+
If unsure, say Y.
568+
569+
config HISILICON_ERRATUM_161600802
570+
bool "Hip07 161600802: Erroneous redistributor VLPI base"
571+
default y
572+
help
573+
The HiSilicon Hip07 SoC usees the wrong redistributor base
574+
when issued ITS commands such as VMOVP and VMAPP, and requires
575+
a 128kB offset to be applied to the target address in this commands.
576+
577+
If unsure, say Y.
559578
endmenu
560579

561580

‎arch/arm64/Kconfig.platforms

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -161,6 +161,9 @@ config ARCH_SEATTLE
161161
config ARCH_SHMOBILE
162162
bool
163163

164+
config ARCH_SYNQUACER
165+
bool "Socionext SynQuacer SoC Family"
166+
164167
config ARCH_RENESAS
165168
bool "Renesas SoC Platforms"
166169
select ARCH_SHMOBILE

‎arch/arm64/include/asm/arch_gicv3.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,11 @@ static inline void gic_write_ctlr(u32 val)
8787
isb();
8888
}
8989

90+
static inline u32 gic_read_ctlr(void)
91+
{
92+
return read_sysreg_s(SYS_ICC_CTLR_EL1);
93+
}
94+
9095
static inline void gic_write_grpen1(u32 val)
9196
{
9297
write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1);

‎arch/x86/include/asm/irqdomain.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,8 +42,8 @@ extern int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
4242
unsigned int nr_irqs, void *arg);
4343
extern void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
4444
unsigned int nr_irqs);
45-
extern void mp_irqdomain_activate(struct irq_domain *domain,
46-
struct irq_data *irq_data);
45+
extern int mp_irqdomain_activate(struct irq_domain *domain,
46+
struct irq_data *irq_data, bool early);
4747
extern void mp_irqdomain_deactivate(struct irq_domain *domain,
4848
struct irq_data *irq_data);
4949
extern int mp_irqdomain_ioapic_idx(struct irq_domain *domain);

‎arch/x86/kernel/apic/htirq.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -112,8 +112,8 @@ static void htirq_domain_free(struct irq_domain *domain, unsigned int virq,
112112
irq_domain_free_irqs_top(domain, virq, nr_irqs);
113113
}
114114

115-
static void htirq_domain_activate(struct irq_domain *domain,
116-
struct irq_data *irq_data)
115+
static int htirq_domain_activate(struct irq_domain *domain,
116+
struct irq_data *irq_data, bool early)
117117
{
118118
struct ht_irq_msg msg;
119119
struct irq_cfg *cfg = irqd_cfg(irq_data);
@@ -132,6 +132,7 @@ static void htirq_domain_activate(struct irq_domain *domain,
132132
HT_IRQ_LOW_MT_ARBITRATED) |
133133
HT_IRQ_LOW_IRQ_MASKED;
134134
write_ht_irq_msg(irq_data->irq, &msg);
135+
return 0;
135136
}
136137

137138
static void htirq_domain_deactivate(struct irq_domain *domain,

‎arch/x86/kernel/apic/io_apic.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2097,7 +2097,7 @@ static inline void __init check_timer(void)
20972097
unmask_ioapic_irq(irq_get_irq_data(0));
20982098
}
20992099
irq_domain_deactivate_irq(irq_data);
2100-
irq_domain_activate_irq(irq_data);
2100+
irq_domain_activate_irq(irq_data, false);
21012101
if (timer_irq_works()) {
21022102
if (disable_timer_pin_1 > 0)
21032103
clear_IO_APIC_pin(0, pin1);
@@ -2119,7 +2119,7 @@ static inline void __init check_timer(void)
21192119
*/
21202120
replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
21212121
irq_domain_deactivate_irq(irq_data);
2122-
irq_domain_activate_irq(irq_data);
2122+
irq_domain_activate_irq(irq_data, false);
21232123
legacy_pic->unmask(0);
21242124
if (timer_irq_works()) {
21252125
apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
@@ -2978,8 +2978,8 @@ void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
29782978
irq_domain_free_irqs_top(domain, virq, nr_irqs);
29792979
}
29802980

2981-
void mp_irqdomain_activate(struct irq_domain *domain,
2982-
struct irq_data *irq_data)
2981+
int mp_irqdomain_activate(struct irq_domain *domain,
2982+
struct irq_data *irq_data, bool early)
29832983
{
29842984
unsigned long flags;
29852985
struct irq_pin_list *entry;
@@ -2989,6 +2989,7 @@ void mp_irqdomain_activate(struct irq_domain *domain,
29892989
for_each_irq_pin(entry, data->irq_2_pin)
29902990
__ioapic_write_entry(entry->apic, entry->pin, data->entry);
29912991
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2992+
return 0;
29922993
}
29932994

29942995
void mp_irqdomain_deactivate(struct irq_domain *domain,

‎arch/x86/platform/uv/uv_irq.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -127,10 +127,11 @@ static void uv_domain_free(struct irq_domain *domain, unsigned int virq,
127127
* Re-target the irq to the specified CPU and enable the specified MMR located
128128
* on the specified blade to allow the sending of MSIs to the specified CPU.
129129
*/
130-
static void uv_domain_activate(struct irq_domain *domain,
131-
struct irq_data *irq_data)
130+
static int uv_domain_activate(struct irq_domain *domain,
131+
struct irq_data *irq_data, bool early)
132132
{
133133
uv_program_mmr(irqd_cfg(irq_data), irq_data->chip_data);
134+
return 0;
134135
}
135136

136137
/*

‎drivers/gpio/gpio-xgene-sb.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -140,8 +140,9 @@ static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
140140
return irq_create_fwspec_mapping(&fwspec);
141141
}
142142

143-
static void xgene_gpio_sb_domain_activate(struct irq_domain *d,
144-
struct irq_data *irq_data)
143+
static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
144+
struct irq_data *irq_data,
145+
bool early)
145146
{
146147
struct xgene_gpio_sb *priv = d->host_data;
147148
u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
@@ -150,11 +151,12 @@ static void xgene_gpio_sb_domain_activate(struct irq_domain *d,
150151
dev_err(priv->gc.parent,
151152
"Unable to configure XGene GPIO standby pin %d as IRQ\n",
152153
gpio);
153-
return;
154+
return -ENOSPC;
154155
}
155156

156157
xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
157158
gpio * 2, 1);
159+
return 0;
158160
}
159161

160162
static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,

‎drivers/iommu/amd_iommu.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4173,8 +4173,8 @@ static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
41734173
irq_domain_free_irqs_common(domain, virq, nr_irqs);
41744174
}
41754175

4176-
static void irq_remapping_activate(struct irq_domain *domain,
4177-
struct irq_data *irq_data)
4176+
static int irq_remapping_activate(struct irq_domain *domain,
4177+
struct irq_data *irq_data, bool early)
41784178
{
41794179
struct amd_ir_data *data = irq_data->chip_data;
41804180
struct irq_2_irte *irte_info = &data->irq_2_irte;
@@ -4183,6 +4183,7 @@ static void irq_remapping_activate(struct irq_domain *domain,
41834183
if (iommu)
41844184
iommu->irte_ops->activate(data->entry, irte_info->devid,
41854185
irte_info->index);
4186+
return 0;
41864187
}
41874188

41884189
static void irq_remapping_deactivate(struct irq_domain *domain,

‎drivers/iommu/intel_irq_remapping.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1390,12 +1390,13 @@ static void intel_irq_remapping_free(struct irq_domain *domain,
13901390
irq_domain_free_irqs_common(domain, virq, nr_irqs);
13911391
}
13921392

1393-
static void intel_irq_remapping_activate(struct irq_domain *domain,
1394-
struct irq_data *irq_data)
1393+
static int intel_irq_remapping_activate(struct irq_domain *domain,
1394+
struct irq_data *irq_data, bool early)
13951395
{
13961396
struct intel_ir_data *data = irq_data->chip_data;
13971397

13981398
modify_irte(&data->irq_2_iommu, &data->irte_entry);
1399+
return 0;
13991400
}
14001401

14011402
static void intel_irq_remapping_deactivate(struct irq_domain *domain,

‎drivers/irqchip/Kconfig

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
menu "IRQ chip support"
2+
13
config IRQCHIP
24
def_bool y
35
depends on OF_IRQ
@@ -307,6 +309,7 @@ config EZNPS_GIC
307309
config STM32_EXTI
308310
bool
309311
select IRQ_DOMAIN
312+
select GENERIC_IRQ_CHIP
310313

311314
config QCOM_IRQ_COMBINER
312315
bool "QCOM IRQ combiner support"
@@ -324,3 +327,13 @@ config IRQ_UNIPHIER_AIDET
324327
select IRQ_DOMAIN_HIERARCHY
325328
help
326329
Support for the UniPhier AIDET (ARM Interrupt Detector).
330+
331+
config MESON_IRQ_GPIO
332+
bool "Meson GPIO Interrupt Multiplexer"
333+
depends on ARCH_MESON
334+
select IRQ_DOMAIN
335+
select IRQ_DOMAIN_HIERARCHY
336+
help
337+
Support Meson SoC Family GPIO Interrupt Multiplexer
338+
339+
endmenu

‎drivers/irqchip/Makefile

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,3 +81,5 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
8181
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
8282
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
8383
obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
84+
obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o
85+
obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o

‎drivers/irqchip/irq-aspeed-i2c-ic.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -76,8 +76,8 @@ static int __init aspeed_i2c_ic_of_init(struct device_node *node,
7676
return -ENOMEM;
7777

7878
i2c_ic->base = of_iomap(node, 0);
79-
if (IS_ERR(i2c_ic->base)) {
80-
ret = PTR_ERR(i2c_ic->base);
79+
if (!i2c_ic->base) {
80+
ret = -ENOMEM;
8181
goto err_free_ic;
8282
}
8383

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