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wildea01wildea01
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Merge branch 'for-rmk/perf' into for-rmk/virt/kvm/core
2 parents 9931fac + 9dcbf46 commit 6abc749

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6 files changed

+75
-49
lines changed

6 files changed

+75
-49
lines changed

‎arch/arm/include/asm/cputype.h

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,24 @@ extern unsigned int processor_id;
6464
#define read_cpuid_ext(reg) 0
6565
#endif
6666

67+
#define ARM_CPU_IMP_ARM 0x41
68+
#define ARM_CPU_IMP_INTEL 0x69
69+
70+
#define ARM_CPU_PART_ARM1136 0xB360
71+
#define ARM_CPU_PART_ARM1156 0xB560
72+
#define ARM_CPU_PART_ARM1176 0xB760
73+
#define ARM_CPU_PART_ARM11MPCORE 0xB020
74+
#define ARM_CPU_PART_CORTEX_A8 0xC080
75+
#define ARM_CPU_PART_CORTEX_A9 0xC090
76+
#define ARM_CPU_PART_CORTEX_A5 0xC050
77+
#define ARM_CPU_PART_CORTEX_A15 0xC0F0
78+
#define ARM_CPU_PART_CORTEX_A7 0xC070
79+
80+
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
81+
#define ARM_CPU_XSCALE_ARCH_V1 0x2000
82+
#define ARM_CPU_XSCALE_ARCH_V2 0x4000
83+
#define ARM_CPU_XSCALE_ARCH_V3 0x6000
84+
6785
/*
6886
* The CPU ID never changes at run time, so we might as well tell the
6987
* compiler that it's constant. Use this function to read the CPU ID
@@ -74,6 +92,21 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
7492
return read_cpuid(CPUID_ID);
7593
}
7694

95+
static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
96+
{
97+
return (read_cpuid_id() & 0xFF000000) >> 24;
98+
}
99+
100+
static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
101+
{
102+
return read_cpuid_id() & 0xFFF0;
103+
}
104+
105+
static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
106+
{
107+
return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
108+
}
109+
77110
static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
78111
{
79112
return read_cpuid(CPUID_CACHETYPE);

‎arch/arm/kernel/perf_event.c

Lines changed: 3 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -149,12 +149,6 @@ u64 armpmu_event_update(struct perf_event *event)
149149
static void
150150
armpmu_read(struct perf_event *event)
151151
{
152-
struct hw_perf_event *hwc = &event->hw;
153-
154-
/* Don't read disabled counters! */
155-
if (hwc->idx < 0)
156-
return;
157-
158152
armpmu_event_update(event);
159153
}
160154

@@ -207,8 +201,6 @@ armpmu_del(struct perf_event *event, int flags)
207201
struct hw_perf_event *hwc = &event->hw;
208202
int idx = hwc->idx;
209203

210-
WARN_ON(idx < 0);
211-
212204
armpmu_stop(event, PERF_EF_UPDATE);
213205
hw_events->events[idx] = NULL;
214206
clear_bit(idx, hw_events->used_mask);
@@ -358,7 +350,7 @@ __hw_perf_event_init(struct perf_event *event)
358350
{
359351
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
360352
struct hw_perf_event *hwc = &event->hw;
361-
int mapping, err;
353+
int mapping;
362354

363355
mapping = armpmu->map_event(event);
364356

@@ -407,14 +399,12 @@ __hw_perf_event_init(struct perf_event *event)
407399
local64_set(&hwc->period_left, hwc->sample_period);
408400
}
409401

410-
err = 0;
411402
if (event->group_leader != event) {
412-
err = validate_group(event);
413-
if (err)
403+
if (validate_group(event) != 0);
414404
return -EINVAL;
415405
}
416406

417-
return err;
407+
return 0;
418408
}
419409

420410
static int armpmu_event_init(struct perf_event *event)

‎arch/arm/kernel/perf_event_cpu.c

Lines changed: 27 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
147147
cpu_pmu->free_irq = cpu_pmu_free_irq;
148148

149149
/* Ensure the PMU has sane values out of reset. */
150-
if (cpu_pmu && cpu_pmu->reset)
150+
if (cpu_pmu->reset)
151151
on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
152152
}
153153

@@ -201,48 +201,46 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = {
201201
static int probe_current_pmu(struct arm_pmu *pmu)
202202
{
203203
int cpu = get_cpu();
204-
unsigned long cpuid = read_cpuid_id();
205-
unsigned long implementor = (cpuid & 0xFF000000) >> 24;
206-
unsigned long part_number = (cpuid & 0xFFF0);
204+
unsigned long implementor = read_cpuid_implementor();
205+
unsigned long part_number = read_cpuid_part_number();
207206
int ret = -ENODEV;
208207

209208
pr_info("probing PMU on CPU %d\n", cpu);
210209

211210
/* ARM Ltd CPUs. */
212-
if (0x41 == implementor) {
211+
if (implementor == ARM_CPU_IMP_ARM) {
213212
switch (part_number) {
214-
case 0xB360: /* ARM1136 */
215-
case 0xB560: /* ARM1156 */
216-
case 0xB760: /* ARM1176 */
213+
case ARM_CPU_PART_ARM1136:
214+
case ARM_CPU_PART_ARM1156:
215+
case ARM_CPU_PART_ARM1176:
217216
ret = armv6pmu_init(pmu);
218217
break;
219-
case 0xB020: /* ARM11mpcore */
218+
case ARM_CPU_PART_ARM11MPCORE:
220219
ret = armv6mpcore_pmu_init(pmu);
221220
break;
222-
case 0xC080: /* Cortex-A8 */
221+
case ARM_CPU_PART_CORTEX_A8:
223222
ret = armv7_a8_pmu_init(pmu);
224223
break;
225-
case 0xC090: /* Cortex-A9 */
224+
case ARM_CPU_PART_CORTEX_A9:
226225
ret = armv7_a9_pmu_init(pmu);
227226
break;
228-
case 0xC050: /* Cortex-A5 */
227+
case ARM_CPU_PART_CORTEX_A5:
229228
ret = armv7_a5_pmu_init(pmu);
230229
break;
231-
case 0xC0F0: /* Cortex-A15 */
230+
case ARM_CPU_PART_CORTEX_A15:
232231
ret = armv7_a15_pmu_init(pmu);
233232
break;
234-
case 0xC070: /* Cortex-A7 */
233+
case ARM_CPU_PART_CORTEX_A7:
235234
ret = armv7_a7_pmu_init(pmu);
236235
break;
237236
}
238237
/* Intel CPUs [xscale]. */
239-
} else if (0x69 == implementor) {
240-
part_number = (cpuid >> 13) & 0x7;
241-
switch (part_number) {
242-
case 1:
238+
} else if (implementor == ARM_CPU_IMP_INTEL) {
239+
switch (xscale_cpu_arch_version()) {
240+
case ARM_CPU_XSCALE_ARCH_V1:
243241
ret = xscale1pmu_init(pmu);
244242
break;
245-
case 2:
243+
case ARM_CPU_XSCALE_ARCH_V2:
246244
ret = xscale2pmu_init(pmu);
247245
break;
248246
}
@@ -279,17 +277,22 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
279277
}
280278

281279
if (ret) {
282-
pr_info("failed to register PMU devices!");
283-
kfree(pmu);
284-
return ret;
280+
pr_info("failed to probe PMU!");
281+
goto out_free;
285282
}
286283

287284
cpu_pmu = pmu;
288285
cpu_pmu->plat_device = pdev;
289286
cpu_pmu_init(cpu_pmu);
290-
armpmu_register(cpu_pmu, PERF_TYPE_RAW);
287+
ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
291288

292-
return 0;
289+
if (!ret)
290+
return 0;
291+
292+
out_free:
293+
pr_info("failed to register PMU devices!");
294+
kfree(pmu);
295+
return ret;
293296
}
294297

295298
static struct platform_driver cpu_pmu_driver = {

‎arch/arm/kernel/perf_event_v6.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
106106
},
107107
[C(OP_WRITE)] = {
108108
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
109-
[C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
109+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
110110
},
111111
[C(OP_PREFETCH)] = {
112112
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
259259
},
260260
[C(OP_WRITE)] = {
261261
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
262-
[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
262+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
263263
},
264264
[C(OP_PREFETCH)] = {
265265
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,

‎arch/arm/kernel/perf_event_v7.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
157157
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
158158
},
159159
[C(OP_WRITE)] = {
160-
[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
161-
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
160+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
161+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
162162
},
163163
[C(OP_PREFETCH)] = {
164164
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
282282
},
283283
[C(OP_WRITE)] = {
284284
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
285-
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
285+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
286286
},
287287
[C(OP_PREFETCH)] = {
288288
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
399399
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
400400
},
401401
[C(OP_WRITE)] = {
402-
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
403-
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
402+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
403+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
404404
},
405405
/*
406406
* The prefetch counters don't differentiate between the I
@@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
527527
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
528528
},
529529
[C(OP_WRITE)] = {
530-
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
531-
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
530+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
531+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
532532
},
533533
[C(OP_PREFETCH)] = {
534534
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
651651
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
652652
},
653653
[C(OP_WRITE)] = {
654-
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
655-
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
654+
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
655+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
656656
},
657657
[C(OP_PREFETCH)] = {
658658
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,

‎arch/arm/kernel/perf_event_xscale.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
8383
},
8484
[C(OP_WRITE)] = {
8585
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
86-
[C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
86+
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
8787
},
8888
[C(OP_PREFETCH)] = {
8989
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,

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