@@ -14,12 +14,7 @@ Required Properties:
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- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
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- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
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- - reg: A list of base address and length of each memory resource, one for
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- each entry in the reg-names property.
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- - reg-names: Name of the memory resources. The DU requires one memory
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- resource for the DU core (named "du") and one memory resource for each
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- LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
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- index).
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+ - reg: the memory-mapped I/O registers base address and length
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- interrupt-parent: phandle of the parent interrupt controller.
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- interrupts: Interrupt specifiers for the DU interrupts.
@@ -29,14 +24,13 @@ Required Properties:
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- clock-names: Name of the clocks. This property is model-dependent.
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- R8A7779 uses a single functional clock. The clock doesn't need to be
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named.
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- - All other DU instances use one functional clock per channel and one
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- clock per LVDS encoder (if available). The functional clocks must be
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- named "du.x" with "x" being the channel numerical index. The LVDS clocks
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- must be named "lvds.x" with "x" being the LVDS encoder numerical index.
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- - In addition to the functional and encoder clocks, all DU versions also
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- support externally supplied pixel clocks. Those clocks are optional.
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- When supplied they must be named "dclkin.x" with "x" being the input
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- clock numerical index.
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+ - All other DU instances use one functional clock per channel The
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+ functional clocks must be named "du.x" with "x" being the channel
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+ numerical index.
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+ - In addition to the functional clocks, all DU versions also support
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+ externally supplied pixel clocks. Those clocks are optional. When
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+ supplied they must be named "dclkin.x" with "x" being the input clock
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+ numerical index.
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- vsps: A list of phandle and channel index tuples to the VSPs that handle
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the memory interfaces for the DU channels. The phandle identifies the VSP
@@ -69,19 +63,16 @@ Example: R8A7795 (R-Car H3) ES2.0 DU
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du: display@feb00000 {
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compatible = "renesas,du-r8a7795";
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- reg = <0 0xfeb00000 0 0x80000>,
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- <0 0xfeb90000 0 0x14>;
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- reg-names = "du", "lvds.0";
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+ reg = <0 0xfeb00000 0 0x80000>;
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 722>,
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- <&cpg CPG_MOD 721>,
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- <&cpg CPG_MOD 727>;
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- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
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+ <&cpg CPG_MOD 721>;
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+ clock-names = "du.0", "du.1", "du.2", "du.3";
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vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
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ports {
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