ptp: clockmatrix: Fix u8 -> u16, DPLL_WF_TIMER and DPLL_WP_TIMER are 2-byte registers

Min Li · NipaLocal · commit 6e57f93b5c5b · 2023-12-01T07:00:49.000-08:00
Signed-off-by: Min Li &lt;min.li.xe@renesas.com&gt;
Signed-off-by: NipaLocal &lt;nipa@local&gt;
diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c
@@ -1396,18 +1396,18 @@ static int idtcm_set_pll_mode(struct idtcm_channel *channel,
 	struct idtcm *idtcm = channel->idtcm;
 	int err;
 	u8 dpll_mode;
-	u8 timeout = 0;
+	u8 buf[2] = {0};
 
 	/* Setup WF/WP timer for phase pull-in to work correctly */
 	err = idtcm_write(idtcm, channel->dpll_n, DPLL_WF_TIMER,
-			  &timeout, sizeof(timeout));
+			  buf, sizeof(buf));
 	if (err)
 		return err;
 
 	if (mode == PLL_MODE_WRITE_PHASE)
-		timeout = 160;
+		buf[0] = 160;
 	err = idtcm_write(idtcm, channel->dpll_n, DPLL_WP_TIMER,
-			  &timeout, sizeof(timeout));
+			  buf, sizeof(buf));
 	if (err)
 		return err;
 
