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27 | 27 | #define AT803X_MMD_ACCESS_CONTROL 0x0D
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28 | 28 | #define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
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29 | 29 | #define AT803X_FUNC_DATA 0x4003
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| 30 | +#define AT803X_INER 0x0012 |
| 31 | +#define AT803X_INER_INIT 0xec00 |
| 32 | +#define AT803X_INSR 0x0013 |
30 | 33 | #define AT803X_DEBUG_ADDR 0x1D
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31 | 34 | #define AT803X_DEBUG_DATA 0x1E
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32 | 35 | #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
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@@ -191,6 +194,31 @@ static int at803x_config_init(struct phy_device *phydev)
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191 | 194 | return 0;
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192 | 195 | }
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193 | 196 |
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| 197 | +static int at803x_ack_interrupt(struct phy_device *phydev) |
| 198 | +{ |
| 199 | + int err; |
| 200 | + |
| 201 | + err = phy_read(phydev, AT803X_INSR); |
| 202 | + |
| 203 | + return (err < 0) ? err : 0; |
| 204 | +} |
| 205 | + |
| 206 | +static int at803x_config_intr(struct phy_device *phydev) |
| 207 | +{ |
| 208 | + int err; |
| 209 | + int value; |
| 210 | + |
| 211 | + value = phy_read(phydev, AT803X_INER); |
| 212 | + |
| 213 | + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
| 214 | + err = phy_write(phydev, AT803X_INER, |
| 215 | + value | AT803X_INER_INIT); |
| 216 | + else |
| 217 | + err = phy_write(phydev, AT803X_INER, 0); |
| 218 | + |
| 219 | + return err; |
| 220 | +} |
| 221 | + |
194 | 222 | static struct phy_driver at803x_driver[] = {
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195 | 223 | {
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196 | 224 | /* ATHEROS 8035 */
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@@ -240,6 +268,8 @@ static struct phy_driver at803x_driver[] = {
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240 | 268 | .flags = PHY_HAS_INTERRUPT,
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241 | 269 | .config_aneg = genphy_config_aneg,
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242 | 270 | .read_status = genphy_read_status,
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| 271 | + .ack_interrupt = &at803x_ack_interrupt, |
| 272 | + .config_intr = &at803x_config_intr, |
243 | 273 | .driver = {
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244 | 274 | .owner = THIS_MODULE,
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245 | 275 | },
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