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davem330davem330
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Merge branch 'hns3-ethtool-dump'
Salil Mehta says: ==================== Adds VF/PF PCIe reg dump(ethtool -d) support to HNS3 driver This patchset adds VF/PF PCIe register dump support to HNS3 VF and PF driver using "ethtool -d" command. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2 parents d1420bb + ea4750c commit 77ac327

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4 files changed

+345
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lines changed

4 files changed

+345
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‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

Lines changed: 115 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,62 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
4848

4949
MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
5050

51+
static const u32 cmdq_reg_addr_list[] = {HCLGE_CMDQ_TX_ADDR_L_REG,
52+
HCLGE_CMDQ_TX_ADDR_H_REG,
53+
HCLGE_CMDQ_TX_DEPTH_REG,
54+
HCLGE_CMDQ_TX_TAIL_REG,
55+
HCLGE_CMDQ_TX_HEAD_REG,
56+
HCLGE_CMDQ_RX_ADDR_L_REG,
57+
HCLGE_CMDQ_RX_ADDR_H_REG,
58+
HCLGE_CMDQ_RX_DEPTH_REG,
59+
HCLGE_CMDQ_RX_TAIL_REG,
60+
HCLGE_CMDQ_RX_HEAD_REG,
61+
HCLGE_VECTOR0_CMDQ_SRC_REG,
62+
HCLGE_CMDQ_INTR_STS_REG,
63+
HCLGE_CMDQ_INTR_EN_REG,
64+
HCLGE_CMDQ_INTR_GEN_REG};
65+
66+
static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
67+
HCLGE_VECTOR0_OTER_EN_REG,
68+
HCLGE_MISC_RESET_STS_REG,
69+
HCLGE_MISC_VECTOR_INT_STS,
70+
HCLGE_GLOBAL_RESET_REG,
71+
HCLGE_FUN_RST_ING,
72+
HCLGE_GRO_EN_REG};
73+
74+
static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG,
75+
HCLGE_RING_RX_ADDR_H_REG,
76+
HCLGE_RING_RX_BD_NUM_REG,
77+
HCLGE_RING_RX_BD_LENGTH_REG,
78+
HCLGE_RING_RX_MERGE_EN_REG,
79+
HCLGE_RING_RX_TAIL_REG,
80+
HCLGE_RING_RX_HEAD_REG,
81+
HCLGE_RING_RX_FBD_NUM_REG,
82+
HCLGE_RING_RX_OFFSET_REG,
83+
HCLGE_RING_RX_FBD_OFFSET_REG,
84+
HCLGE_RING_RX_STASH_REG,
85+
HCLGE_RING_RX_BD_ERR_REG,
86+
HCLGE_RING_TX_ADDR_L_REG,
87+
HCLGE_RING_TX_ADDR_H_REG,
88+
HCLGE_RING_TX_BD_NUM_REG,
89+
HCLGE_RING_TX_PRIORITY_REG,
90+
HCLGE_RING_TX_TC_REG,
91+
HCLGE_RING_TX_MERGE_EN_REG,
92+
HCLGE_RING_TX_TAIL_REG,
93+
HCLGE_RING_TX_HEAD_REG,
94+
HCLGE_RING_TX_FBD_NUM_REG,
95+
HCLGE_RING_TX_OFFSET_REG,
96+
HCLGE_RING_TX_EBD_NUM_REG,
97+
HCLGE_RING_TX_EBD_OFFSET_REG,
98+
HCLGE_RING_TX_BD_ERR_REG,
99+
HCLGE_RING_EN_REG};
100+
101+
static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
102+
HCLGE_TQP_INTR_GL0_REG,
103+
HCLGE_TQP_INTR_GL1_REG,
104+
HCLGE_TQP_INTR_GL2_REG,
105+
HCLGE_TQP_INTR_RL_REG};
106+
51107
static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
52108
"App Loopback test",
53109
"Serdes serial Loopback test",
@@ -7637,8 +7693,15 @@ static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
76377693
return 0;
76387694
}
76397695

7696+
#define MAX_SEPARATE_NUM 4
7697+
#define SEPARATOR_VALUE 0xFFFFFFFF
7698+
#define REG_NUM_PER_LINE 4
7699+
#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
7700+
76407701
static int hclge_get_regs_len(struct hnae3_handle *handle)
76417702
{
7703+
int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
7704+
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
76427705
struct hclge_vport *vport = hclge_get_vport(handle);
76437706
struct hclge_dev *hdev = vport->back;
76447707
u32 regs_num_32_bit, regs_num_64_bit;
@@ -7651,15 +7714,25 @@ static int hclge_get_regs_len(struct hnae3_handle *handle)
76517714
return -EOPNOTSUPP;
76527715
}
76537716

7654-
return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
7717+
cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
7718+
common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
7719+
ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
7720+
tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
7721+
7722+
return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps +
7723+
tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE +
7724+
regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
76557725
}
76567726

76577727
static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
76587728
void *data)
76597729
{
7730+
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
76607731
struct hclge_vport *vport = hclge_get_vport(handle);
76617732
struct hclge_dev *hdev = vport->back;
76627733
u32 regs_num_32_bit, regs_num_64_bit;
7734+
int i, j, reg_um, separator_num;
7735+
u32 *reg = data;
76637736
int ret;
76647737

76657738
*version = hdev->fw_version;
@@ -7671,16 +7744,53 @@ static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
76717744
return;
76727745
}
76737746

7674-
ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
7747+
/* fetching per-PF registers valus from PF PCIe register space */
7748+
reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
7749+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7750+
for (i = 0; i < reg_um; i++)
7751+
*reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
7752+
for (i = 0; i < separator_num; i++)
7753+
*reg++ = SEPARATOR_VALUE;
7754+
7755+
reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
7756+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7757+
for (i = 0; i < reg_um; i++)
7758+
*reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]);
7759+
for (i = 0; i < separator_num; i++)
7760+
*reg++ = SEPARATOR_VALUE;
7761+
7762+
reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
7763+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7764+
for (j = 0; j < kinfo->num_tqps; j++) {
7765+
for (i = 0; i < reg_um; i++)
7766+
*reg++ = hclge_read_dev(&hdev->hw,
7767+
ring_reg_addr_list[i] +
7768+
0x200 * j);
7769+
for (i = 0; i < separator_num; i++)
7770+
*reg++ = SEPARATOR_VALUE;
7771+
}
7772+
7773+
reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
7774+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
7775+
for (j = 0; j < hdev->num_msi_used - 1; j++) {
7776+
for (i = 0; i < reg_um; i++)
7777+
*reg++ = hclge_read_dev(&hdev->hw,
7778+
tqp_intr_reg_addr_list[i] +
7779+
4 * j);
7780+
for (i = 0; i < separator_num; i++)
7781+
*reg++ = SEPARATOR_VALUE;
7782+
}
7783+
7784+
/* fetching PF common registers values from firmware */
7785+
ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg);
76757786
if (ret) {
76767787
dev_err(&hdev->pdev->dev,
76777788
"Get 32 bit register failed, ret = %d.\n", ret);
76787789
return;
76797790
}
76807791

7681-
data = (u32 *)data + regs_num_32_bit;
7682-
ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
7683-
data);
7792+
reg += regs_num_32_bit;
7793+
ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg);
76847794
if (ret)
76857795
dev_err(&hdev->pdev->dev,
76867796
"Get 64 bit register failed, ret = %d.\n", ret);

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,62 @@
2828
#define HCLGE_VECTOR_REG_OFFSET 0x4
2929
#define HCLGE_VECTOR_VF_OFFSET 0x100000
3030

31+
#define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000
32+
#define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004
33+
#define HCLGE_CMDQ_TX_DEPTH_REG 0x27008
34+
#define HCLGE_CMDQ_TX_TAIL_REG 0x27010
35+
#define HCLGE_CMDQ_TX_HEAD_REG 0x27014
36+
#define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018
37+
#define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C
38+
#define HCLGE_CMDQ_RX_DEPTH_REG 0x27020
39+
#define HCLGE_CMDQ_RX_TAIL_REG 0x27024
40+
#define HCLGE_CMDQ_RX_HEAD_REG 0x27028
41+
#define HCLGE_CMDQ_INTR_SRC_REG 0x27100
42+
#define HCLGE_CMDQ_INTR_STS_REG 0x27104
43+
#define HCLGE_CMDQ_INTR_EN_REG 0x27108
44+
#define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
45+
46+
/* bar registers for common func */
47+
#define HCLGE_VECTOR0_OTER_EN_REG 0x20600
48+
#define HCLGE_RAS_OTHER_STS_REG 0x20B00
49+
#define HCLGE_FUNC_RESET_STS_REG 0x20C00
50+
#define HCLGE_GRO_EN_REG 0x28000
51+
52+
/* bar registers for rcb */
53+
#define HCLGE_RING_RX_ADDR_L_REG 0x80000
54+
#define HCLGE_RING_RX_ADDR_H_REG 0x80004
55+
#define HCLGE_RING_RX_BD_NUM_REG 0x80008
56+
#define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
57+
#define HCLGE_RING_RX_MERGE_EN_REG 0x80014
58+
#define HCLGE_RING_RX_TAIL_REG 0x80018
59+
#define HCLGE_RING_RX_HEAD_REG 0x8001C
60+
#define HCLGE_RING_RX_FBD_NUM_REG 0x80020
61+
#define HCLGE_RING_RX_OFFSET_REG 0x80024
62+
#define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
63+
#define HCLGE_RING_RX_STASH_REG 0x80030
64+
#define HCLGE_RING_RX_BD_ERR_REG 0x80034
65+
#define HCLGE_RING_TX_ADDR_L_REG 0x80040
66+
#define HCLGE_RING_TX_ADDR_H_REG 0x80044
67+
#define HCLGE_RING_TX_BD_NUM_REG 0x80048
68+
#define HCLGE_RING_TX_PRIORITY_REG 0x8004C
69+
#define HCLGE_RING_TX_TC_REG 0x80050
70+
#define HCLGE_RING_TX_MERGE_EN_REG 0x80054
71+
#define HCLGE_RING_TX_TAIL_REG 0x80058
72+
#define HCLGE_RING_TX_HEAD_REG 0x8005C
73+
#define HCLGE_RING_TX_FBD_NUM_REG 0x80060
74+
#define HCLGE_RING_TX_OFFSET_REG 0x80064
75+
#define HCLGE_RING_TX_EBD_NUM_REG 0x80068
76+
#define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
77+
#define HCLGE_RING_TX_BD_ERR_REG 0x80074
78+
#define HCLGE_RING_EN_REG 0x80090
79+
80+
/* bar registers for tqp interrupt */
81+
#define HCLGE_TQP_INTR_CTRL_REG 0x20000
82+
#define HCLGE_TQP_INTR_GL0_REG 0x20100
83+
#define HCLGE_TQP_INTR_GL1_REG 0x20200
84+
#define HCLGE_TQP_INTR_GL2_REG 0x20300
85+
#define HCLGE_TQP_INTR_RL_REG 0x20900
86+
3187
#define HCLGE_RSS_IND_TBL_SIZE 512
3288
#define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
3389
#define HCLGE_RSS_KEY_SIZE 40

‎drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,58 @@ static const struct pci_device_id ae_algovf_pci_tbl[] = {
2323

2424
MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
2525

26+
static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
27+
HCLGEVF_CMDQ_TX_ADDR_H_REG,
28+
HCLGEVF_CMDQ_TX_DEPTH_REG,
29+
HCLGEVF_CMDQ_TX_TAIL_REG,
30+
HCLGEVF_CMDQ_TX_HEAD_REG,
31+
HCLGEVF_CMDQ_RX_ADDR_L_REG,
32+
HCLGEVF_CMDQ_RX_ADDR_H_REG,
33+
HCLGEVF_CMDQ_RX_DEPTH_REG,
34+
HCLGEVF_CMDQ_RX_TAIL_REG,
35+
HCLGEVF_CMDQ_RX_HEAD_REG,
36+
HCLGEVF_VECTOR0_CMDQ_SRC_REG,
37+
HCLGEVF_CMDQ_INTR_STS_REG,
38+
HCLGEVF_CMDQ_INTR_EN_REG,
39+
HCLGEVF_CMDQ_INTR_GEN_REG};
40+
41+
static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
42+
HCLGEVF_RST_ING,
43+
HCLGEVF_GRO_EN_REG};
44+
45+
static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
46+
HCLGEVF_RING_RX_ADDR_H_REG,
47+
HCLGEVF_RING_RX_BD_NUM_REG,
48+
HCLGEVF_RING_RX_BD_LENGTH_REG,
49+
HCLGEVF_RING_RX_MERGE_EN_REG,
50+
HCLGEVF_RING_RX_TAIL_REG,
51+
HCLGEVF_RING_RX_HEAD_REG,
52+
HCLGEVF_RING_RX_FBD_NUM_REG,
53+
HCLGEVF_RING_RX_OFFSET_REG,
54+
HCLGEVF_RING_RX_FBD_OFFSET_REG,
55+
HCLGEVF_RING_RX_STASH_REG,
56+
HCLGEVF_RING_RX_BD_ERR_REG,
57+
HCLGEVF_RING_TX_ADDR_L_REG,
58+
HCLGEVF_RING_TX_ADDR_H_REG,
59+
HCLGEVF_RING_TX_BD_NUM_REG,
60+
HCLGEVF_RING_TX_PRIORITY_REG,
61+
HCLGEVF_RING_TX_TC_REG,
62+
HCLGEVF_RING_TX_MERGE_EN_REG,
63+
HCLGEVF_RING_TX_TAIL_REG,
64+
HCLGEVF_RING_TX_HEAD_REG,
65+
HCLGEVF_RING_TX_FBD_NUM_REG,
66+
HCLGEVF_RING_TX_OFFSET_REG,
67+
HCLGEVF_RING_TX_EBD_NUM_REG,
68+
HCLGEVF_RING_TX_EBD_OFFSET_REG,
69+
HCLGEVF_RING_TX_BD_ERR_REG,
70+
HCLGEVF_RING_EN_REG};
71+
72+
static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
73+
HCLGEVF_TQP_INTR_GL0_REG,
74+
HCLGEVF_TQP_INTR_GL1_REG,
75+
HCLGEVF_TQP_INTR_GL2_REG,
76+
HCLGEVF_TQP_INTR_RL_REG};
77+
2678
static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
2779
struct hnae3_handle *handle)
2880
{
@@ -2473,6 +2525,72 @@ static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
24732525
return hdev->reset_count;
24742526
}
24752527

2528+
#define MAX_SEPARATE_NUM 4
2529+
#define SEPARATOR_VALUE 0xFFFFFFFF
2530+
#define REG_NUM_PER_LINE 4
2531+
#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
2532+
2533+
static int hclgevf_get_regs_len(struct hnae3_handle *handle)
2534+
{
2535+
int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
2536+
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2537+
2538+
cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
2539+
common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
2540+
ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
2541+
tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
2542+
2543+
return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
2544+
tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
2545+
}
2546+
2547+
static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
2548+
void *data)
2549+
{
2550+
struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2551+
int i, j, reg_um, separator_num;
2552+
u32 *reg = data;
2553+
2554+
*version = hdev->fw_version;
2555+
2556+
/* fetching per-VF registers values from VF PCIe register space */
2557+
reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
2558+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2559+
for (i = 0; i < reg_um; i++)
2560+
*reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
2561+
for (i = 0; i < separator_num; i++)
2562+
*reg++ = SEPARATOR_VALUE;
2563+
2564+
reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
2565+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2566+
for (i = 0; i < reg_um; i++)
2567+
*reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
2568+
for (i = 0; i < separator_num; i++)
2569+
*reg++ = SEPARATOR_VALUE;
2570+
2571+
reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
2572+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2573+
for (j = 0; j < hdev->num_tqps; j++) {
2574+
for (i = 0; i < reg_um; i++)
2575+
*reg++ = hclgevf_read_dev(&hdev->hw,
2576+
ring_reg_addr_list[i] +
2577+
0x200 * j);
2578+
for (i = 0; i < separator_num; i++)
2579+
*reg++ = SEPARATOR_VALUE;
2580+
}
2581+
2582+
reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
2583+
separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2584+
for (j = 0; j < hdev->num_msi_used - 1; j++) {
2585+
for (i = 0; i < reg_um; i++)
2586+
*reg++ = hclgevf_read_dev(&hdev->hw,
2587+
tqp_intr_reg_addr_list[i] +
2588+
4 * j);
2589+
for (i = 0; i < separator_num; i++)
2590+
*reg++ = SEPARATOR_VALUE;
2591+
}
2592+
}
2593+
24762594
static const struct hnae3_ae_ops hclgevf_ops = {
24772595
.init_ae_dev = hclgevf_init_ae_dev,
24782596
.uninit_ae_dev = hclgevf_uninit_ae_dev,
@@ -2514,6 +2632,8 @@ static const struct hnae3_ae_ops hclgevf_ops = {
25142632
.set_default_reset_request = hclgevf_set_def_reset_request,
25152633
.get_channels = hclgevf_get_channels,
25162634
.get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
2635+
.get_regs_len = hclgevf_get_regs_len,
2636+
.get_regs = hclgevf_get_regs,
25172637
.get_status = hclgevf_get_status,
25182638
.get_ksettings_an_result = hclgevf_get_ksettings_an_result,
25192639
.get_media_type = hclgevf_get_media_type,

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