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net: ethernet: realtek: atp: checkpatch errors and warnings corrected
Several warnings and errors of coding style rules corrected. Compile tested. Signed-off-by: Roberto Medina <robertoxmed@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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  • drivers/net/ethernet/realtek

1 file changed

+127
-119
lines changed

‎drivers/net/ethernet/realtek/atp.h

Lines changed: 127 additions & 119 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,10 @@
66

77
/* The header prepended to received packets. */
88
struct rx_header {
9-
ushort pad; /* Pad. */
10-
ushort rx_count;
11-
ushort rx_status; /* Unknown bit assignments :-<. */
12-
ushort cur_addr; /* Apparently the current buffer address(?) */
9+
ushort pad; /* Pad. */
10+
ushort rx_count;
11+
ushort rx_status; /* Unknown bit assignments :-<. */
12+
ushort cur_addr; /* Apparently the current buffer address(?) */
1313
};
1414

1515
#define PAR_DATA 0
@@ -29,22 +29,25 @@ struct rx_header {
2929
#define RdAddr 0xC0
3030
#define HNib 0x10
3131

32-
enum page0_regs
33-
{
34-
/* The first six registers hold the ethernet physical station address. */
35-
PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
36-
TxCNT0 = 6, TxCNT1 = 7, /* The transmit byte count. */
37-
TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */
38-
ISR = 10, IMR = 11, /* Interrupt status and mask. */
39-
CMR1 = 12, /* Command register 1. */
40-
CMR2 = 13, /* Command register 2. */
41-
MODSEL = 14, /* Mode select register. */
42-
MAR = 14, /* Memory address register (?). */
43-
CMR2_h = 0x1d, };
44-
45-
enum eepage_regs
46-
{ PROM_CMD = 6, PROM_DATA = 7 }; /* Note that PROM_CMD is in the "high" bits. */
32+
enum page0_regs {
33+
/* The first six registers hold
34+
* the ethernet physical station address.
35+
*/
36+
PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
37+
TxCNT0 = 6, TxCNT1 = 7, /* The transmit byte count. */
38+
TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */
39+
ISR = 10, IMR = 11, /* Interrupt status and mask. */
40+
CMR1 = 12, /* Command register 1. */
41+
CMR2 = 13, /* Command register 2. */
42+
MODSEL = 14, /* Mode select register. */
43+
MAR = 14, /* Memory address register (?). */
44+
CMR2_h = 0x1d,
45+
};
4746

47+
enum eepage_regs {
48+
PROM_CMD = 6,
49+
PROM_DATA = 7 /* Note that PROM_CMD is in the "high" bits. */
50+
};
4851

4952
#define ISR_TxOK 0x01
5053
#define ISR_RxOK 0x04
@@ -72,170 +75,175 @@ enum eepage_regs
7275
#define CMR2h_Normal 2 /* Accept physical and broadcast address. */
7376
#define CMR2h_PROMISC 3 /* Promiscuous mode. */
7477

75-
/* An inline function used below: it differs from inb() by explicitly return an unsigned
76-
char, saving a truncation. */
78+
/* An inline function used below: it differs from inb() by explicitly
79+
* return an unsigned char, saving a truncation.
80+
*/
7781
static inline unsigned char inbyte(unsigned short port)
7882
{
79-
unsigned char _v;
80-
__asm__ __volatile__ ("inb %w1,%b0" :"=a" (_v):"d" (port));
81-
return _v;
83+
unsigned char _v;
84+
85+
__asm__ __volatile__ ("inb %w1,%b0" : "=a" (_v) : "d" (port));
86+
return _v;
8287
}
8388

8489
/* Read register OFFSET.
85-
This command should always be terminated with read_end(). */
90+
* This command should always be terminated with read_end().
91+
*/
8692
static inline unsigned char read_nibble(short port, unsigned char offset)
8793
{
88-
unsigned char retval;
89-
outb(EOC+offset, port + PAR_DATA);
90-
outb(RdAddr+offset, port + PAR_DATA);
91-
inbyte(port + PAR_STATUS); /* Settling time delay */
92-
retval = inbyte(port + PAR_STATUS);
93-
outb(EOC+offset, port + PAR_DATA);
94-
95-
return retval;
94+
unsigned char retval;
95+
96+
outb(EOC+offset, port + PAR_DATA);
97+
outb(RdAddr+offset, port + PAR_DATA);
98+
inbyte(port + PAR_STATUS); /* Settling time delay */
99+
retval = inbyte(port + PAR_STATUS);
100+
outb(EOC+offset, port + PAR_DATA);
101+
102+
return retval;
96103
}
97104

98105
/* Functions for bulk data read. The interrupt line is always disabled. */
99106
/* Get a byte using read mode 0, reading data from the control lines. */
100107
static inline unsigned char read_byte_mode0(short ioaddr)
101108
{
102-
unsigned char low_nib;
103-
104-
outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
105-
inbyte(ioaddr + PAR_STATUS);
106-
low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
107-
outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
108-
inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
109-
inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
110-
return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
109+
unsigned char low_nib;
110+
111+
outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
112+
inbyte(ioaddr + PAR_STATUS);
113+
low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
114+
outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
115+
inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
116+
inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
117+
return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
111118
}
112119

113120
/* The same as read_byte_mode0(), but does multiple inb()s for stability. */
114121
static inline unsigned char read_byte_mode2(short ioaddr)
115122
{
116-
unsigned char low_nib;
117-
118-
outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
119-
inbyte(ioaddr + PAR_STATUS);
120-
low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
121-
outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
122-
inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
123-
return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
123+
unsigned char low_nib;
124+
125+
outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
126+
inbyte(ioaddr + PAR_STATUS);
127+
low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
128+
outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
129+
inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
130+
return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
124131
}
125132

126133
/* Read a byte through the data register. */
127134
static inline unsigned char read_byte_mode4(short ioaddr)
128135
{
129-
unsigned char low_nib;
136+
unsigned char low_nib;
130137

131-
outb(RdAddr | MAR, ioaddr + PAR_DATA);
132-
low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
133-
outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
134-
return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
138+
outb(RdAddr | MAR, ioaddr + PAR_DATA);
139+
low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
140+
outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
141+
return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
135142
}
136143

137144
/* Read a byte through the data register, double reading to allow settling. */
138145
static inline unsigned char read_byte_mode6(short ioaddr)
139146
{
140-
unsigned char low_nib;
141-
142-
outb(RdAddr | MAR, ioaddr + PAR_DATA);
143-
inbyte(ioaddr + PAR_STATUS);
144-
low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
145-
outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
146-
inbyte(ioaddr + PAR_STATUS);
147-
return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
147+
unsigned char low_nib;
148+
149+
outb(RdAddr | MAR, ioaddr + PAR_DATA);
150+
inbyte(ioaddr + PAR_STATUS);
151+
low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
152+
outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
153+
inbyte(ioaddr + PAR_STATUS);
154+
return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
148155
}
149156

150157
static inline void
151158
write_reg(short port, unsigned char reg, unsigned char value)
152159
{
153-
unsigned char outval;
154-
outb(EOC | reg, port + PAR_DATA);
155-
outval = WrAddr | reg;
156-
outb(outval, port + PAR_DATA);
157-
outb(outval, port + PAR_DATA); /* Double write for PS/2. */
158-
159-
outval &= 0xf0;
160-
outval |= value;
161-
outb(outval, port + PAR_DATA);
162-
outval &= 0x1f;
163-
outb(outval, port + PAR_DATA);
164-
outb(outval, port + PAR_DATA);
165-
166-
outb(EOC | outval, port + PAR_DATA);
160+
unsigned char outval;
161+
162+
outb(EOC | reg, port + PAR_DATA);
163+
outval = WrAddr | reg;
164+
outb(outval, port + PAR_DATA);
165+
outb(outval, port + PAR_DATA); /* Double write for PS/2. */
166+
167+
outval &= 0xf0;
168+
outval |= value;
169+
outb(outval, port + PAR_DATA);
170+
outval &= 0x1f;
171+
outb(outval, port + PAR_DATA);
172+
outb(outval, port + PAR_DATA);
173+
174+
outb(EOC | outval, port + PAR_DATA);
167175
}
168176

169177
static inline void
170178
write_reg_high(short port, unsigned char reg, unsigned char value)
171179
{
172-
unsigned char outval = EOC | HNib | reg;
180+
unsigned char outval = EOC | HNib | reg;
173181

174-
outb(outval, port + PAR_DATA);
175-
outval &= WrAddr | HNib | 0x0f;
176-
outb(outval, port + PAR_DATA);
177-
outb(outval, port + PAR_DATA); /* Double write for PS/2. */
182+
outb(outval, port + PAR_DATA);
183+
outval &= WrAddr | HNib | 0x0f;
184+
outb(outval, port + PAR_DATA);
185+
outb(outval, port + PAR_DATA); /* Double write for PS/2. */
178186

179-
outval = WrAddr | HNib | value;
180-
outb(outval, port + PAR_DATA);
181-
outval &= HNib | 0x0f; /* HNib | value */
182-
outb(outval, port + PAR_DATA);
183-
outb(outval, port + PAR_DATA);
187+
outval = WrAddr | HNib | value;
188+
outb(outval, port + PAR_DATA);
189+
outval &= HNib | 0x0f; /* HNib | value */
190+
outb(outval, port + PAR_DATA);
191+
outb(outval, port + PAR_DATA);
184192

185-
outb(EOC | HNib | outval, port + PAR_DATA);
193+
outb(EOC | HNib | outval, port + PAR_DATA);
186194
}
187195

188196
/* Write a byte out using nibble mode. The low nibble is written first. */
189197
static inline void
190198
write_reg_byte(short port, unsigned char reg, unsigned char value)
191199
{
192-
unsigned char outval;
193-
outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */
194-
outval = WrAddr | reg;
195-
outb(outval, port + PAR_DATA);
196-
outb(outval, port + PAR_DATA); /* Double write for PS/2. */
197-
198-
outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
199-
outb(value & 0x0f, port + PAR_DATA);
200-
value >>= 4;
201-
outb(value, port + PAR_DATA);
202-
outb(0x10 | value, port + PAR_DATA);
203-
outb(0x10 | value, port + PAR_DATA);
204-
205-
outb(EOC | value, port + PAR_DATA); /* Reset the address register. */
200+
unsigned char outval;
201+
202+
outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */
203+
outval = WrAddr | reg;
204+
outb(outval, port + PAR_DATA);
205+
outb(outval, port + PAR_DATA); /* Double write for PS/2. */
206+
207+
outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
208+
outb(value & 0x0f, port + PAR_DATA);
209+
value >>= 4;
210+
outb(value, port + PAR_DATA);
211+
outb(0x10 | value, port + PAR_DATA);
212+
outb(0x10 | value, port + PAR_DATA);
213+
214+
outb(EOC | value, port + PAR_DATA); /* Reset the address register. */
206215
}
207216

208-
/*
209-
* Bulk data writes to the packet buffer. The interrupt line remains enabled.
217+
/* Bulk data writes to the packet buffer. The interrupt line remains enabled.
210218
* The first, faster method uses only the dataport (data modes 0, 2 & 4).
211219
* The second (backup) method uses data and control regs (modes 1, 3 & 5).
212220
* It should only be needed when there is skew between the individual data
213221
* lines.
214222
*/
215223
static inline void write_byte_mode0(short ioaddr, unsigned char value)
216224
{
217-
outb(value & 0x0f, ioaddr + PAR_DATA);
218-
outb((value>>4) | 0x10, ioaddr + PAR_DATA);
225+
outb(value & 0x0f, ioaddr + PAR_DATA);
226+
outb((value>>4) | 0x10, ioaddr + PAR_DATA);
219227
}
220228

221229
static inline void write_byte_mode1(short ioaddr, unsigned char value)
222230
{
223-
outb(value & 0x0f, ioaddr + PAR_DATA);
224-
outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
225-
outb((value>>4) | 0x10, ioaddr + PAR_DATA);
226-
outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
231+
outb(value & 0x0f, ioaddr + PAR_DATA);
232+
outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
233+
outb((value>>4) | 0x10, ioaddr + PAR_DATA);
234+
outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
227235
}
228236

229237
/* Write 16bit VALUE to the packet buffer: the same as above just doubled. */
230238
static inline void write_word_mode0(short ioaddr, unsigned short value)
231239
{
232-
outb(value & 0x0f, ioaddr + PAR_DATA);
233-
value >>= 4;
234-
outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
235-
value >>= 4;
236-
outb(value & 0x0f, ioaddr + PAR_DATA);
237-
value >>= 4;
238-
outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
240+
outb(value & 0x0f, ioaddr + PAR_DATA);
241+
value >>= 4;
242+
outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
243+
value >>= 4;
244+
outb(value & 0x0f, ioaddr + PAR_DATA);
245+
value >>= 4;
246+
outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
239247
}
240248

241249
/* EEPROM_Ctrl bits. */
@@ -248,10 +256,10 @@ static inline void write_word_mode0(short ioaddr, unsigned short value)
248256

249257
/* Delay between EEPROM clock transitions. */
250258
#define eeprom_delay(ticks) \
251-
do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
259+
do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; } } while (0)
252260

253261
/* The EEPROM commands include the alway-set leading bit. */
254262
#define EE_WRITE_CMD(offset) (((5 << 6) + (offset)) << 17)
255-
#define EE_READ(offset) (((6 << 6) + (offset)) << 17)
263+
#define EE_READ(offset) (((6 << 6) + (offset)) << 17)
256264
#define EE_ERASE(offset) (((7 << 6) + (offset)) << 17)
257265
#define EE_CMD_SIZE 27 /* The command+address+data size. */

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