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alexaringholtmann
alexaring
authored and
holtmann
committed
mrf24j40: replace magic numbers
This patch replaces some magic numbers with defines for register bits, mask and shifts. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
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‎drivers/net/ieee802154/mrf24j40.c

Lines changed: 98 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,11 @@
2626

2727
/* MRF24J40 Short Address Registers */
2828
#define REG_RXMCR 0x00 /* Receive MAC control */
29+
#define BIT_PROMI BIT(0)
30+
#define BIT_ERRPKT BIT(1)
31+
#define BIT_NOACKRSP BIT(5)
32+
#define BIT_PANCOORD BIT(3)
33+
2934
#define REG_PANIDL 0x01 /* PAN ID (low) */
3035
#define REG_PANIDH 0x02 /* PAN ID (high) */
3136
#define REG_SADRL 0x03 /* Short address (low) */
@@ -41,6 +46,11 @@
4146
#define REG_RXFLUSH 0x0D
4247
#define REG_ORDER 0x10
4348
#define REG_TXMCR 0x11 /* Transmit MAC control */
49+
#define TXMCR_MIN_BE_SHIFT 3
50+
#define TXMCR_MIN_BE_MASK 0x18
51+
#define TXMCR_CSMA_RETRIES_SHIFT 0
52+
#define TXMCR_CSMA_RETRIES_MASK 0x07
53+
4454
#define REG_ACKTMOUT 0x12
4555
#define REG_ESLOTG1 0x13
4656
#define REG_SYMTICKL 0x14
@@ -50,6 +60,9 @@
5060
#define REG_PACON2 0x18 /* Power Amplifier Control */
5161
#define REG_TXBCON0 0x1A
5262
#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
63+
#define BIT_TXNTRIG BIT(0)
64+
#define BIT_TXNACKREQ BIT(2)
65+
5366
#define REG_TXG1CON 0x1C
5467
#define REG_TXG2CON 0x1D
5568
#define REG_ESLOTG23 0x1E
@@ -70,25 +83,61 @@
7083
#define REG_TXSTBL 0x2E /* TX Stabilization */
7184
#define REG_RXSR 0x30
7285
#define REG_INTSTAT 0x31 /* Interrupt Status */
86+
#define BIT_TXNIF BIT(0)
87+
#define BIT_RXIF BIT(3)
88+
7389
#define REG_INTCON 0x32 /* Interrupt Control */
90+
#define BIT_TXNIE BIT(0)
91+
#define BIT_RXIE BIT(3)
92+
7493
#define REG_GPIO 0x33 /* GPIO */
7594
#define REG_TRISGPIO 0x34 /* GPIO direction */
7695
#define REG_SLPACK 0x35
7796
#define REG_RFCTL 0x36 /* RF Control Mode Register */
97+
#define BIT_RFRST BIT(2)
98+
7899
#define REG_SECCR2 0x37
79100
#define REG_BBREG0 0x38
80101
#define REG_BBREG1 0x39 /* Baseband Registers */
102+
#define BIT_RXDECINV BIT(2)
103+
81104
#define REG_BBREG2 0x3A /* */
105+
#define BBREG2_CCA_MODE_SHIFT 6
106+
#define BBREG2_CCA_MODE_MASK 0xc0
107+
82108
#define REG_BBREG3 0x3B
83109
#define REG_BBREG4 0x3C
84110
#define REG_BBREG6 0x3E /* */
85111
#define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
86112

87113
/* MRF24J40 Long Address Registers */
88114
#define REG_RFCON0 0x200 /* RF Control Registers */
115+
#define RFCON0_CH_SHIFT 4
116+
#define RFCON0_CH_MASK 0xf0
117+
#define RFOPT_RECOMMEND 3
118+
89119
#define REG_RFCON1 0x201
90120
#define REG_RFCON2 0x202
91121
#define REG_RFCON3 0x203
122+
123+
#define TXPWRL_MASK 0xc0
124+
#define TXPWRL_SHIFT 6
125+
#define TXPWRL_30 0x3
126+
#define TXPWRL_20 0x2
127+
#define TXPWRL_10 0x1
128+
#define TXPWRL_0 0x0
129+
130+
#define TXPWRS_MASK 0x38
131+
#define TXPWRS_SHIFT 3
132+
#define TXPWRS_6_3 0x7
133+
#define TXPWRS_4_9 0x6
134+
#define TXPWRS_3_7 0x5
135+
#define TXPWRS_2_8 0x4
136+
#define TXPWRS_1_9 0x3
137+
#define TXPWRS_1_2 0x2
138+
#define TXPWRS_0_5 0x1
139+
#define TXPWRS_0 0x0
140+
92141
#define REG_RFCON5 0x205
93142
#define REG_RFCON6 0x206
94143
#define REG_RFCON7 0x207
@@ -99,6 +148,8 @@
99148
#define REG_RFSTATE 0x20F
100149
#define REG_RSSI 0x210
101150
#define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
151+
#define BIT_INTEDGE BIT(1)
152+
102153
#define REG_SLPCON1 0x220
103154
#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
104155
#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
@@ -493,11 +544,11 @@ static void write_tx_buf_complete(void *context)
493544
{
494545
struct mrf24j40 *devrec = context;
495546
__le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
496-
u8 val = 0x01;
547+
u8 val = BIT_TXNTRIG;
497548
int ret;
498549

499550
if (ieee802154_is_ackreq(fc))
500-
val |= 0x04;
551+
val |= BIT_TXNACKREQ;
501552

502553
devrec->tx_post_msg.complete = NULL;
503554
devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
@@ -564,7 +615,7 @@ static int mrf24j40_start(struct ieee802154_hw *hw)
564615

565616
/* Clear TXNIE and RXIE. Enable interrupts */
566617
return regmap_update_bits(devrec->regmap_short, REG_INTCON,
567-
0x01 | 0x08, 0x00);
618+
BIT_TXNIE | BIT_RXIE, 0);
568619
}
569620

570621
static void mrf24j40_stop(struct ieee802154_hw *hw)
@@ -574,8 +625,8 @@ static void mrf24j40_stop(struct ieee802154_hw *hw)
574625
dev_dbg(printdev(devrec), "stop\n");
575626

576627
/* Set TXNIE and RXIE. Disable Interrupts */
577-
regmap_update_bits(devrec->regmap_short, REG_INTCON, 0x01 | 0x08,
578-
0x01 | 0x08);
628+
regmap_update_bits(devrec->regmap_short, REG_INTCON,
629+
BIT_TXNIE | BIT_TXNIE, BIT_TXNIE | BIT_TXNIE);
579630
}
580631

581632
static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
@@ -591,17 +642,19 @@ static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
591642
WARN_ON(channel > MRF24J40_CHAN_MAX);
592643

593644
/* Set Channel TODO */
594-
val = (channel-11) << 4 | 0x03;
595-
ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, 0xf0, val);
645+
val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND;
646+
ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0,
647+
RFCON0_CH_MASK, val);
596648
if (ret)
597649
return ret;
598650

599651
/* RF Reset */
600-
ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x04);
652+
ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST,
653+
BIT_RFRST);
601654
if (ret)
602655
return ret;
603656

604-
ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x00);
657+
ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0);
605658
if (!ret)
606659
udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
607660

@@ -664,11 +717,11 @@ static int mrf24j40_filter(struct ieee802154_hw *hw,
664717
int ret;
665718

666719
if (filt->pan_coord)
667-
val = 0x8;
720+
val = BIT_PANCOORD;
668721
else
669-
val = 0x0;
670-
ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x8,
671-
val);
722+
val = 0;
723+
ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
724+
BIT_PANCOORD, val);
672725
if (ret)
673726
return ret;
674727

@@ -772,7 +825,7 @@ static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
772825
devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
773826
devrec->rx_trx.len = 2;
774827
devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
775-
devrec->rx_buf[1] = 0x04; /* SET RXDECINV */
828+
devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */
776829

777830
return spi_async(devrec->spi, &devrec->rx_msg);
778831
}
@@ -785,11 +838,13 @@ mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
785838
u8 val;
786839

787840
/* min_be */
788-
val = min_be << 3;
841+
val = min_be << TXMCR_MIN_BE_SHIFT;
789842
/* csma backoffs */
790-
val |= retries;
843+
val |= retries << TXMCR_CSMA_RETRIES_SHIFT;
791844

792-
return regmap_update_bits(devrec->regmap_short, REG_TXMCR, 0x1f, val);
845+
return regmap_update_bits(devrec->regmap_short, REG_TXMCR,
846+
TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK,
847+
val);
793848
}
794849

795850
static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
@@ -819,8 +874,9 @@ static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
819874
return -EINVAL;
820875
}
821876

822-
return regmap_update_bits(devrec->regmap_short, REG_BBREG2, 0xc0,
823-
val << 6);
877+
return regmap_update_bits(devrec->regmap_short, REG_BBREG2,
878+
BBREG2_CCA_MODE_MASK,
879+
val << BBREG2_CCA_MODE_SHIFT);
824880
}
825881

826882
/* array for representing ed levels */
@@ -878,50 +934,52 @@ static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm)
878934
u8 val;
879935

880936
if (0 >= mbm && mbm > -1000) {
881-
val = 0;
937+
val = TXPWRL_0 << TXPWRL_SHIFT;
882938
small_scale = mbm;
883939
} else if (-1000 >= mbm && mbm > -2000) {
884-
val = 0x40;
940+
val = TXPWRL_10 << TXPWRL_SHIFT;
885941
small_scale = mbm + 1000;
886942
} else if (-2000 >= mbm && mbm > -3000) {
887-
val = 0x80;
943+
val = TXPWRL_20 << TXPWRL_SHIFT;
888944
small_scale = mbm + 2000;
889945
} else if (-3000 >= mbm && mbm > -4000) {
890-
val = 0xc0;
946+
val = TXPWRL_30 << TXPWRL_SHIFT;
891947
small_scale = mbm + 3000;
892948
} else {
893949
return -EINVAL;
894950
}
895951

896952
switch (small_scale) {
897953
case 0:
954+
val |= (TXPWRS_0 << TXPWRS_SHIFT);
898955
break;
899956
case -50:
900-
val |= 0x08;
957+
val |= (TXPWRS_0_5 << TXPWRS_SHIFT);
901958
break;
902959
case -120:
903-
val |= 0x10;
960+
val |= (TXPWRS_1_2 << TXPWRS_SHIFT);
904961
break;
905962
case -190:
906-
val |= 0x18;
963+
val |= (TXPWRS_1_9 << TXPWRS_SHIFT);
907964
break;
908965
case -280:
909-
val |= 0x20;
966+
val |= (TXPWRS_2_8 << TXPWRS_SHIFT);
910967
break;
911968
case -370:
912-
val |= 0x28;
969+
val |= (TXPWRS_3_7 << TXPWRS_SHIFT);
913970
break;
914971
case -490:
915-
val |= 0x30;
972+
val |= (TXPWRS_4_9 << TXPWRS_SHIFT);
916973
break;
917974
case -630:
918-
val |= 0x38;
975+
val |= (TXPWRS_6_3 << TXPWRS_SHIFT);
919976
break;
920977
default:
921978
return -EINVAL;
922979
}
923980

924-
return regmap_update_bits(devrec->regmap_long, REG_RFCON3, 0xf8, val);
981+
return regmap_update_bits(devrec->regmap_long, REG_RFCON3,
982+
TXPWRL_MASK | TXPWRS_MASK, val);
925983
}
926984

927985
static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
@@ -931,12 +989,14 @@ static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on)
931989

932990
if (on) {
933991
/* set PROMI, ERRPKT and NOACKRSP */
934-
ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x23,
935-
0x23);
992+
ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
993+
BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
994+
BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP);
936995
} else {
937996
/* clear PROMI, ERRPKT and NOACKRSP */
938-
ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x23,
939-
0x00);
997+
ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR,
998+
BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP,
999+
0);
9401000
}
9411001

9421002
return ret;
@@ -965,11 +1025,11 @@ static void mrf24j40_intstat_complete(void *context)
9651025
enable_irq(devrec->spi->irq);
9661026

9671027
/* Check for TX complete */
968-
if (intstat & 0x1)
1028+
if (intstat & BIT_TXNIF)
9691029
ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
9701030

9711031
/* Check for Rx */
972-
if (intstat & 0x8)
1032+
if (intstat & BIT_RXIF)
9731033
mrf24j40_handle_rx(devrec);
9741034
}
9751035

@@ -1095,7 +1155,7 @@ static int mrf24j40_hw_init(struct mrf24j40 *devrec)
10951155
case IRQ_TYPE_LEVEL_HIGH:
10961156
/* set interrupt polarity to rising */
10971157
ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0,
1098-
0x02, 0x02);
1158+
BIT_INTEDGE, BIT_INTEDGE);
10991159
if (ret)
11001160
goto err_ret;
11011161
break;

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