dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property

andreamerello · vinodkoul · commit 7df54dbeb055 · 2019-01-07T09:53:11.000+05:30
The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add documentation for it.

Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Signed-off-by: Andrea Merello &lt;andrea.merello@gmail.com&gt;
Reviewed-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Reviewed-by: Rob Herring &lt;robh+dt@kernel.org&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -41,6 +41,10 @@ Optional properties:
 - xlnx,include-sg: Tells configured for Scatter-mode in
 	the hardware.
 Optional properties for AXI DMA:
+- xlnx,sg-length-width: Should be set to the width in bits of the length
+	register as configured in h/w. Takes values {8...26}. If the property
+	is missing or invalid then the default value 23 is used. This is the
+	maximum value that is supported by all IP versions.
 - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
