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Amit Nischalbebarino
Amit Nischal
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bebarino
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clk: qcom: Configure the RCGs to a safe source as needed
For some root clock generators, there could be child branches which are controlled by an entity other than application processor subsystem. For such RCGs, as per application processor subsystem clock driver, all of its downstream clocks are disabled and RCG is in disabled state but in reality downstream clocks can be left enabled before. So in this scenario, when RCG is disabled as per clock driver's point of view and when rate scaling request comes before downstream clock enable request, then RCG fails to update its configuration because in reality RCG is on and it expects its new source to already be in enable state but in reality new source is off. In order to avoid having the RCG to go into an invalid state, add support to update the CFG, M, N and D registers during set_rate() without configuration update and defer the actual RCG configuration update to be done during clk_enable() as at this point of time, both its new parent and safe source will be already enabled and RCG can safely switch to new parent. During clk_disable() request, configure it to safe source as both its parents, safe source and current parent will be enabled and RCG can safely execute a switch. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/qcom/clk-rcg.h

Lines changed: 5 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,5 @@
1-
/*
2-
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
3-
*
4-
* This software is licensed under the terms of the GNU General Public
5-
* License version 2, as published by the Free Software Foundation, and
6-
* may be copied, distributed, and modified under those terms.
7-
*
8-
* This program is distributed in the hope that it will be useful,
9-
* but WITHOUT ANY WARRANTY; without even the implied warranty of
10-
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11-
* GNU General Public License for more details.
12-
*/
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
133

144
#ifndef __QCOM_CLK_RCG_H__
155
#define __QCOM_CLK_RCG_H__
@@ -144,6 +134,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
144134
* @cmd_rcgr: corresponds to *_CMD_RCGR
145135
* @mnd_width: number of bits in m/n/d values
146136
* @hid_width: number of bits in half integer divider
137+
* @safe_src_index: safe src index value
147138
* @parent_map: map from software's parent index to hardware's src_sel field
148139
* @freq_tbl: frequency table
149140
* @clkr: regmap clock handle
@@ -153,6 +144,7 @@ struct clk_rcg2 {
153144
u32 cmd_rcgr;
154145
u8 mnd_width;
155146
u8 hid_width;
147+
u8 safe_src_index;
156148
const struct parent_map *parent_map;
157149
const struct freq_tbl *freq_tbl;
158150
struct clk_regmap clkr;
@@ -167,5 +159,6 @@ extern const struct clk_ops clk_byte_ops;
167159
extern const struct clk_ops clk_byte2_ops;
168160
extern const struct clk_ops clk_pixel_ops;
169161
extern const struct clk_ops clk_gfx3d_ops;
162+
extern const struct clk_ops clk_rcg2_shared_ops;
170163

171164
#endif

‎drivers/clk/qcom/clk-rcg2.c

Lines changed: 150 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,6 @@
1+
// SPDX-License-Identifier: GPL-2.0
12
/*
23
* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.
3-
*
4-
* This software is licensed under the terms of the GNU General Public
5-
* License version 2, as published by the Free Software Foundation, and
6-
* may be copied, distributed, and modified under those terms.
7-
*
8-
* This program is distributed in the hope that it will be useful,
9-
* but WITHOUT ANY WARRANTY; without even the implied warranty of
10-
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11-
* GNU General Public License for more details.
124
*/
135

146
#include <linux/kernel.h>
@@ -249,7 +241,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
249241
return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
250242
}
251243

252-
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
244+
static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
253245
{
254246
u32 cfg, mask;
255247
struct clk_hw *hw = &rcg->clkr.hw;
@@ -282,8 +274,16 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
282274
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
283275
if (rcg->mnd_width && f->n && (f->m != f->n))
284276
cfg |= CFG_MODE_DUAL_EDGE;
285-
ret = regmap_update_bits(rcg->clkr.regmap,
286-
rcg->cmd_rcgr + CFG_REG, mask, cfg);
277+
278+
return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
279+
mask, cfg);
280+
}
281+
282+
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
283+
{
284+
int ret;
285+
286+
ret = __clk_rcg2_configure(rcg, f);
287287
if (ret)
288288
return ret;
289289

@@ -790,3 +790,141 @@ const struct clk_ops clk_gfx3d_ops = {
790790
.determine_rate = clk_gfx3d_determine_rate,
791791
};
792792
EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
793+
794+
static int clk_rcg2_set_force_enable(struct clk_hw *hw)
795+
{
796+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
797+
const char *name = clk_hw_get_name(hw);
798+
int ret, count;
799+
800+
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
801+
CMD_ROOT_EN, CMD_ROOT_EN);
802+
if (ret)
803+
return ret;
804+
805+
/* wait for RCG to turn ON */
806+
for (count = 500; count > 0; count--) {
807+
if (clk_rcg2_is_enabled(hw))
808+
return 0;
809+
810+
udelay(1);
811+
}
812+
813+
pr_err("%s: RCG did not turn on\n", name);
814+
return -ETIMEDOUT;
815+
}
816+
817+
static int clk_rcg2_clear_force_enable(struct clk_hw *hw)
818+
{
819+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
820+
821+
return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
822+
CMD_ROOT_EN, 0);
823+
}
824+
825+
static int
826+
clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
827+
{
828+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
829+
int ret;
830+
831+
ret = clk_rcg2_set_force_enable(hw);
832+
if (ret)
833+
return ret;
834+
835+
ret = clk_rcg2_configure(rcg, f);
836+
if (ret)
837+
return ret;
838+
839+
return clk_rcg2_clear_force_enable(hw);
840+
}
841+
842+
static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
843+
unsigned long parent_rate)
844+
{
845+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
846+
const struct freq_tbl *f;
847+
848+
f = qcom_find_freq(rcg->freq_tbl, rate);
849+
if (!f)
850+
return -EINVAL;
851+
852+
/*
853+
* In case clock is disabled, update the CFG, M, N and D registers
854+
* and don't hit the update bit of CMD register.
855+
*/
856+
if (!__clk_is_enabled(hw->clk))
857+
return __clk_rcg2_configure(rcg, f);
858+
859+
return clk_rcg2_shared_force_enable_clear(hw, f);
860+
}
861+
862+
static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,
863+
unsigned long rate, unsigned long parent_rate, u8 index)
864+
{
865+
return clk_rcg2_shared_set_rate(hw, rate, parent_rate);
866+
}
867+
868+
static int clk_rcg2_shared_enable(struct clk_hw *hw)
869+
{
870+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
871+
int ret;
872+
873+
/*
874+
* Set the update bit because required configuration has already
875+
* been written in clk_rcg2_shared_set_rate()
876+
*/
877+
ret = clk_rcg2_set_force_enable(hw);
878+
if (ret)
879+
return ret;
880+
881+
ret = update_config(rcg);
882+
if (ret)
883+
return ret;
884+
885+
return clk_rcg2_clear_force_enable(hw);
886+
}
887+
888+
static void clk_rcg2_shared_disable(struct clk_hw *hw)
889+
{
890+
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
891+
u32 cfg;
892+
893+
/*
894+
* Store current configuration as switching to safe source would clear
895+
* the SRC and DIV of CFG register
896+
*/
897+
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
898+
899+
/*
900+
* Park the RCG at a safe configuration - sourced off of safe source.
901+
* Force enable and disable the RCG while configuring it to safeguard
902+
* against any update signal coming from the downstream clock.
903+
* The current parent is still prepared and enabled at this point, and
904+
* the safe source is always on while application processor subsystem
905+
* is online. Therefore, the RCG can safely switch its parent.
906+
*/
907+
clk_rcg2_set_force_enable(hw);
908+
909+
regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
910+
rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
911+
912+
update_config(rcg);
913+
914+
clk_rcg2_clear_force_enable(hw);
915+
916+
/* Write back the stored configuration corresponding to current rate */
917+
regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
918+
}
919+
920+
const struct clk_ops clk_rcg2_shared_ops = {
921+
.enable = clk_rcg2_shared_enable,
922+
.disable = clk_rcg2_shared_disable,
923+
.get_parent = clk_rcg2_get_parent,
924+
.set_parent = clk_rcg2_set_parent,
925+
.recalc_rate = clk_rcg2_recalc_rate,
926+
.determine_rate = clk_rcg2_determine_rate,
927+
.set_rate = clk_rcg2_shared_set_rate,
928+
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
929+
};
930+
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);

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