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Merge branch 'mvpp2-add-TX-interrupts-support'
Thomas Petazzoni says: ==================== net: mvpp2: add TX interrupts support So far, the mvpp2 driver was using an hrtimer to handle TX completion. This patch series adds support for using TX interrupts (for each CPU) on PPv2.2, the variant of the IP used on Marvell Armada 7K/8K. Dave: this version can be applied right away, it no longer depends on Antoine's patch series. Antoine series had some comments, so he will have to respin later on. Therefore, let's merge this smaller patch series first. Changes since v1: - Rebased on top of net-next, instead of on top of Antoine's series. - Removed the Device Tree patch, as it shouldn't go through the net tree. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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‎Documentation/devicetree/bindings/net/marvell-pp2.txt

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,10 @@ Optional properties (port):
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- marvell,loopback: port is loopback mode
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- phy: a phandle to a phy node defining the PHY address (as the reg
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property, a single integer).
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- interrupt-names: if more than a single interrupt for rx is given, must
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be the name associated to the interrupts listed. Valid
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names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3",
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"rx-shared".
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Example for marvell,armada-375-pp2:
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@@ -80,19 +84,37 @@ cpm_ethernet: ethernet@0 {
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clock-names = "pp_clk", "gop_clk", "gp_clk";
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eth0: eth0 {
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared";
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port-id = <0>;
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gop-port-id = <0>;
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};
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eth1: eth1 {
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared";
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port-id = <1>;
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gop-port-id = <2>;
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};
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eth2: eth2 {
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared";
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port-id = <2>;
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gop-port-id = <3>;
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};

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