Skip to content

Commit 82bc596

Browse files
Niklas Söderlundmchehab
Niklas Söderlund
authored and
mchehab
committed
media: rcar-csi2: Add support for C-PHY on R-Car V4H
Add support for C-PHY on R-Car V4H. While the V4H supports both D-PHY and C-PHY this patch only adds support for the C-PHY mode due to lack of documentation and hardware to test on. The V4H is the first Gen4 device that is enabled in the rcar-csi2 driver. There is much overlap with the Gen3 driver, the primary difference is in how the receiver is started. The V4H have a much larger register space and some addresses overlap with Gen3. [Sakari Ailus: Use div_u64() to divide a 64-bit integer.] Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
1 parent 34e3d3c commit 82bc596

File tree

1 file changed

+291
-0
lines changed

1 file changed

+291
-0
lines changed

‎drivers/media/platform/renesas/rcar-vin/rcar-csi2.c

Lines changed: 291 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -132,6 +132,111 @@ struct rcar_csi2;
132132
#define PHYFRX_FORCERX_MODE_1 BIT(1)
133133
#define PHYFRX_FORCERX_MODE_0 BIT(0)
134134

135+
/* V4H BASE registers */
136+
#define V4H_N_LANES_REG 0x0004
137+
#define V4H_CSI2_RESETN_REG 0x0008
138+
#define V4H_PHY_MODE_REG 0x001c
139+
#define V4H_PHY_SHUTDOWNZ_REG 0x0040
140+
#define V4H_DPHY_RSTZ_REG 0x0044
141+
#define V4H_FLDC_REG 0x0804
142+
#define V4H_FLDD_REG 0x0808
143+
#define V4H_IDIC_REG 0x0810
144+
#define V4H_PHY_EN_REG 0x2000
145+
146+
#define V4H_ST_PHYST_REG 0x2814
147+
#define V4H_ST_PHYST_ST_PHY_READY BIT(31)
148+
#define V4H_ST_PHYST_ST_STOPSTATE_3 BIT(3)
149+
#define V4H_ST_PHYST_ST_STOPSTATE_2 BIT(2)
150+
#define V4H_ST_PHYST_ST_STOPSTATE_1 BIT(1)
151+
#define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0)
152+
153+
/* V4H PPI registers */
154+
#define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0x21800 + ((n) * 2)) /* n = 0 - 9 */
155+
#define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0x21822
156+
#define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0x2184c
157+
#define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0x21c02
158+
#define V4H_PPI_RW_LPDCOCAL_NREF_REG 0x21c04
159+
#define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0x21c06
160+
#define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a
161+
#define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c
162+
#define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10
163+
#define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c
164+
#define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80
165+
#define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0
166+
167+
/* V4H CORE registers */
168+
#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(n) (0x22040 + ((n) * 2)) /* n = 0 - 15 */
169+
#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(n) (0x22440 + ((n) * 2)) /* n = 0 - 15 */
170+
#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(n) (0x22840 + ((n) * 2)) /* n = 0 - 15 */
171+
#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(n) (0x22c40 + ((n) * 2)) /* n = 0 - 15 */
172+
#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(n) (0x23040 + ((n) * 2)) /* n = 0 - 15 */
173+
#define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */
174+
#define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */
175+
#define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */
176+
#define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400
177+
#define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c
178+
179+
/* V4H C-PHY */
180+
#define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */
181+
#define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */
182+
#define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */
183+
#define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080
184+
#define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */
185+
#define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480
186+
#define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */
187+
#define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880
188+
#define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */
189+
190+
struct rcsi2_cphy_setting {
191+
u16 msps;
192+
u16 rx2;
193+
u16 trio0;
194+
u16 trio1;
195+
u16 trio2;
196+
u16 lane27;
197+
u16 lane29;
198+
};
199+
200+
static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = {
201+
{ .msps = 80, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0134, .trio2 = 0x6a, .lane27 = 0x0000, .lane29 = 0x0a24 },
202+
{ .msps = 100, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x00f5, .trio2 = 0x55, .lane27 = 0x0000, .lane29 = 0x0a24 },
203+
{ .msps = 200, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0077, .trio2 = 0x2b, .lane27 = 0x0000, .lane29 = 0x0a44 },
204+
{ .msps = 300, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x004d, .trio2 = 0x1d, .lane27 = 0x0000, .lane29 = 0x0a44 },
205+
{ .msps = 400, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0038, .trio2 = 0x16, .lane27 = 0x0000, .lane29 = 0x0a64 },
206+
{ .msps = 500, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x002b, .trio2 = 0x12, .lane27 = 0x0000, .lane29 = 0x0a64 },
207+
{ .msps = 600, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0023, .trio2 = 0x0f, .lane27 = 0x0000, .lane29 = 0x0a64 },
208+
{ .msps = 700, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x001d, .trio2 = 0x0d, .lane27 = 0x0000, .lane29 = 0x0a84 },
209+
{ .msps = 800, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0018, .trio2 = 0x0c, .lane27 = 0x0000, .lane29 = 0x0a84 },
210+
{ .msps = 900, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0015, .trio2 = 0x0b, .lane27 = 0x0000, .lane29 = 0x0a84 },
211+
{ .msps = 1000, .rx2 = 0x3e, .trio0 = 0x024a, .trio1 = 0x0012, .trio2 = 0x0a, .lane27 = 0x0400, .lane29 = 0x0a84 },
212+
{ .msps = 1100, .rx2 = 0x44, .trio0 = 0x024a, .trio1 = 0x000f, .trio2 = 0x09, .lane27 = 0x0800, .lane29 = 0x0a84 },
213+
{ .msps = 1200, .rx2 = 0x4a, .trio0 = 0x024a, .trio1 = 0x000e, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0a84 },
214+
{ .msps = 1300, .rx2 = 0x51, .trio0 = 0x024a, .trio1 = 0x000c, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0aa4 },
215+
{ .msps = 1400, .rx2 = 0x57, .trio0 = 0x024a, .trio1 = 0x000b, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 },
216+
{ .msps = 1500, .rx2 = 0x5d, .trio0 = 0x044a, .trio1 = 0x0009, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 },
217+
{ .msps = 1600, .rx2 = 0x63, .trio0 = 0x044a, .trio1 = 0x0008, .trio2 = 0x07, .lane27 = 0x1400, .lane29 = 0x0aa4 },
218+
{ .msps = 1700, .rx2 = 0x6a, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
219+
{ .msps = 1800, .rx2 = 0x70, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
220+
{ .msps = 1900, .rx2 = 0x76, .trio0 = 0x044a, .trio1 = 0x0006, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
221+
{ .msps = 2000, .rx2 = 0x7c, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x06, .lane27 = 0x1800, .lane29 = 0x0aa4 },
222+
{ .msps = 2100, .rx2 = 0x83, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
223+
{ .msps = 2200, .rx2 = 0x89, .trio0 = 0x064a, .trio1 = 0x0004, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
224+
{ .msps = 2300, .rx2 = 0x8f, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
225+
{ .msps = 2400, .rx2 = 0x95, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
226+
{ .msps = 2500, .rx2 = 0x9c, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0aa4 },
227+
{ .msps = 2600, .rx2 = 0xa2, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
228+
{ .msps = 2700, .rx2 = 0xa8, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
229+
{ .msps = 2800, .rx2 = 0xae, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
230+
{ .msps = 2900, .rx2 = 0xb5, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
231+
{ .msps = 3000, .rx2 = 0xbb, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
232+
{ .msps = 3100, .rx2 = 0xc1, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
233+
{ .msps = 3200, .rx2 = 0xc7, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
234+
{ .msps = 3300, .rx2 = 0xce, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
235+
{ .msps = 3400, .rx2 = 0xd4, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
236+
{ .msps = 3500, .rx2 = 0xda, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
237+
{ /* sentinel */ },
238+
};
239+
135240
struct phtw_value {
136241
u16 data;
137242
u16 code;
@@ -537,6 +642,11 @@ static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
537642
iowrite32(data, priv->base + reg);
538643
}
539644

645+
static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data)
646+
{
647+
iowrite16(data, priv->base + reg);
648+
}
649+
540650
static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv)
541651
{
542652
rcsi2_write(priv, PHYCNT_REG, 0);
@@ -644,6 +754,10 @@ static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,
644754
mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
645755
do_div(mbps, lanes * 1000000);
646756

757+
/* Adjust for C-PHY, divide by 2.8. */
758+
if (priv->cphy)
759+
mbps = div_u64(mbps * 5, 14);
760+
647761
return mbps;
648762
}
649763

@@ -833,6 +947,173 @@ static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv)
833947
return 0;
834948
}
835949

950+
static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match)
951+
{
952+
unsigned int timeout;
953+
u32 status;
954+
955+
for (timeout = 0; timeout <= 10; timeout++) {
956+
status = rcsi2_read(priv, V4H_ST_PHYST_REG);
957+
if ((status & match) == match)
958+
return 0;
959+
960+
usleep_range(1000, 2000);
961+
}
962+
963+
return -ETIMEDOUT;
964+
}
965+
966+
static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int msps)
967+
{
968+
const struct rcsi2_cphy_setting *conf;
969+
970+
for (conf = cphy_setting_table_r8a779g0; conf->msps != 0; conf++) {
971+
if (conf->msps > msps)
972+
break;
973+
}
974+
975+
if (!conf->msps) {
976+
dev_err(priv->dev, "Unsupported PHY speed for msps setting (%u Msps)", msps);
977+
return -ERANGE;
978+
}
979+
980+
/* C-PHY specific */
981+
rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0155);
982+
rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), 0x0068);
983+
rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0010);
984+
985+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_LP_0_REG, 0x463c);
986+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_LP_0_REG, 0x463c);
987+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_LP_0_REG, 0x463c);
988+
989+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(0), 0x00d5);
990+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(0), 0x00d5);
991+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(0), 0x00d5);
992+
993+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(1), 0x0013);
994+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(1), 0x0013);
995+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(1), 0x0013);
996+
997+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(5), 0x0013);
998+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(5), 0x0013);
999+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(5), 0x0013);
1000+
1001+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(6), 0x000a);
1002+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(6), 0x000a);
1003+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(6), 0x000a);
1004+
1005+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(2), conf->rx2);
1006+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(2), conf->rx2);
1007+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(2), conf->rx2);
1008+
1009+
rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(2), 0x0001);
1010+
rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(2), 0);
1011+
rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(2), 0x0001);
1012+
rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(2), 0x0001);
1013+
rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(2), 0);
1014+
1015+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0);
1016+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0);
1017+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(0), conf->trio0);
1018+
1019+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(2), conf->trio2);
1020+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(2), conf->trio2);
1021+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(2), conf->trio2);
1022+
1023+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(1), conf->trio1);
1024+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(1), conf->trio1);
1025+
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(1), conf->trio1);
1026+
1027+
/*
1028+
* Configure pin-swap.
1029+
* TODO: This registers is not documented yet, the values should depend
1030+
* on the 'clock-lanes' and 'data-lanes' devicetree properties.
1031+
*/
1032+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG, 0xf5);
1033+
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000);
1034+
1035+
/* Leave Shutdown mode */
1036+
rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0));
1037+
rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0));
1038+
1039+
/* Wait for calibration */
1040+
if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) {
1041+
dev_err(priv->dev, "PHY calibration failed\n");
1042+
return -ETIMEDOUT;
1043+
}
1044+
1045+
/* C-PHY setting - analog programing*/
1046+
rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9), conf->lane29);
1047+
rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(7), conf->lane27);
1048+
1049+
return 0;
1050+
}
1051+
1052+
static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv)
1053+
{
1054+
const struct rcar_csi2_format *format;
1055+
unsigned int lanes;
1056+
int msps;
1057+
int ret;
1058+
1059+
/* Calculate parameters */
1060+
format = rcsi2_code_to_fmt(priv->mf.code);
1061+
if (!format)
1062+
return -EINVAL;
1063+
1064+
ret = rcsi2_get_active_lanes(priv, &lanes);
1065+
if (ret)
1066+
return ret;
1067+
1068+
msps = rcsi2_calc_mbps(priv, format->bpp, lanes);
1069+
if (msps < 0)
1070+
return msps;
1071+
1072+
/* Reset LINK and PHY*/
1073+
rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0);
1074+
rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0);
1075+
rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0);
1076+
1077+
/* PHY static setting */
1078+
rcsi2_write(priv, V4H_PHY_EN_REG, BIT(0));
1079+
rcsi2_write(priv, V4H_FLDC_REG, 0);
1080+
rcsi2_write(priv, V4H_FLDD_REG, 0);
1081+
rcsi2_write(priv, V4H_IDIC_REG, 0);
1082+
rcsi2_write(priv, V4H_PHY_MODE_REG, BIT(0));
1083+
rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1);
1084+
1085+
/* Reset CSI2 */
1086+
rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0));
1087+
1088+
/* Registers static setting through APB */
1089+
/* Common setting */
1090+
rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(0), 0x1bfd);
1091+
rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG, 0x0233);
1092+
rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(6), 0x0027);
1093+
rcsi2_write16(priv, V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG, 0x01f4);
1094+
rcsi2_write16(priv, V4H_PPI_RW_TERMCAL_CFG_0_REG, 0x0013);
1095+
rcsi2_write16(priv, V4H_PPI_RW_OFFSETCAL_CFG_0_REG, 0x0003);
1096+
rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG, 0x004f);
1097+
rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_REG, 0x0320);
1098+
rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG, 0x000f);
1099+
rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG, 0xfe18);
1100+
rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG, 0x0c3c);
1101+
rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG, 0x0105);
1102+
rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x1000);
1103+
rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003);
1104+
1105+
/* C-PHY settings */
1106+
ret = rcsi2_c_phy_setting_v4h(priv, msps);
1107+
if (ret)
1108+
return ret;
1109+
1110+
rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 |
1111+
V4H_ST_PHYST_ST_STOPSTATE_1 |
1112+
V4H_ST_PHYST_ST_STOPSTATE_2);
1113+
1114+
return 0;
1115+
}
1116+
8361117
static int rcsi2_start(struct rcar_csi2 *priv)
8371118
{
8381119
int ret;
@@ -1495,6 +1776,12 @@ static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = {
14951776
.support_dphy = true,
14961777
};
14971778

1779+
static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = {
1780+
.start_receiver = rcsi2_start_receiver_v4h,
1781+
.use_isp = true,
1782+
.support_cphy = true,
1783+
};
1784+
14981785
static const struct of_device_id rcar_csi2_of_table[] = {
14991786
{
15001787
.compatible = "renesas,r8a774a1-csi2",
@@ -1544,6 +1831,10 @@ static const struct of_device_id rcar_csi2_of_table[] = {
15441831
.compatible = "renesas,r8a779a0-csi2",
15451832
.data = &rcar_csi2_info_r8a779a0,
15461833
},
1834+
{
1835+
.compatible = "renesas,r8a779g0-csi2",
1836+
.data = &rcar_csi2_info_r8a779g0,
1837+
},
15471838
{ /* sentinel */ },
15481839
};
15491840
MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);

0 commit comments

Comments
 (0)