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aikmpe
aik
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mpe
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powerpc/powernv/npu: Convert NPU IOMMU helpers to iommu_table_group_ops
At the moment NPU IOMMU is manipulated directly from the IODA2 PCI PE code; PCI PE acts as a master to NPU PE. Soon we will have compound IOMMU groups with several PEs from several different PHB (such as interconnected GPUs and NPUs) so there will be no single master but a one big IOMMU group. This makes a first step and converts an NPU PE with a set of extern function to a table group. This should cause no behavioral change. Note that pnv_npu_release_ownership() has never been implemented. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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3 files changed

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lines changed

‎arch/powerpc/platforms/powernv/npu-dma.c

Lines changed: 27 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -120,9 +120,14 @@ static struct pnv_ioda_pe *get_gpu_pci_dev_and_pe(struct pnv_ioda_pe *npe,
120120
return pe;
121121
}
122122

123-
long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
123+
static long pnv_npu_unset_window(struct iommu_table_group *table_group,
124+
int num);
125+
126+
static long pnv_npu_set_window(struct iommu_table_group *table_group, int num,
124127
struct iommu_table *tbl)
125128
{
129+
struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe,
130+
table_group);
126131
struct pnv_phb *phb = npe->phb;
127132
int64_t rc;
128133
const unsigned long size = tbl->it_indirect_levels ?
@@ -133,7 +138,7 @@ long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
133138

134139
/* NPU has just one TVE so if there is another table, remove it first */
135140
if (npe->table_group.tables[num2])
136-
pnv_npu_unset_window(npe, num2);
141+
pnv_npu_unset_window(&npe->table_group, num2);
137142

138143
pe_info(npe, "Setting up window %llx..%llx pg=%lx\n",
139144
start_addr, start_addr + win_size - 1,
@@ -159,8 +164,10 @@ long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
159164
return 0;
160165
}
161166

162-
long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num)
167+
static long pnv_npu_unset_window(struct iommu_table_group *table_group, int num)
163168
{
169+
struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe,
170+
table_group);
164171
struct pnv_phb *phb = npe->phb;
165172
int64_t rc;
166173

@@ -205,7 +212,8 @@ static void pnv_npu_dma_set_32(struct pnv_ioda_pe *npe)
205212
if (!gpe)
206213
return;
207214

208-
rc = pnv_npu_set_window(npe, 0, gpe->table_group.tables[0]);
215+
rc = pnv_npu_set_window(&npe->table_group, 0,
216+
gpe->table_group.tables[0]);
209217

210218
/*
211219
* NVLink devices use the same TCE table configuration as
@@ -230,7 +238,7 @@ static int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe)
230238
if (phb->type != PNV_PHB_NPU_NVLINK || !npe->pdev)
231239
return -EINVAL;
232240

233-
rc = pnv_npu_unset_window(npe, 0);
241+
rc = pnv_npu_unset_window(&npe->table_group, 0);
234242
if (rc != OPAL_SUCCESS)
235243
return rc;
236244

@@ -283,9 +291,12 @@ void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass)
283291
}
284292
}
285293

294+
#ifdef CONFIG_IOMMU_API
286295
/* Switch ownership from platform code to external user (e.g. VFIO) */
287-
void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
296+
static void pnv_npu_take_ownership(struct iommu_table_group *table_group)
288297
{
298+
struct pnv_ioda_pe *npe = container_of(table_group, struct pnv_ioda_pe,
299+
table_group);
289300
struct pnv_phb *phb = npe->phb;
290301
int64_t rc;
291302

@@ -296,7 +307,7 @@ void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
296307
* if it was enabled at the moment of ownership change.
297308
*/
298309
if (npe->table_group.tables[0]) {
299-
pnv_npu_unset_window(npe, 0);
310+
pnv_npu_unset_window(&npe->table_group, 0);
300311
return;
301312
}
302313

@@ -311,6 +322,12 @@ void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
311322
pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
312323
}
313324

325+
static struct iommu_table_group_ops pnv_pci_npu_ops = {
326+
.set_window = pnv_npu_set_window,
327+
.unset_window = pnv_npu_unset_window,
328+
.take_ownership = pnv_npu_take_ownership,
329+
};
330+
314331
struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
315332
{
316333
struct pnv_phb *phb = npe->phb;
@@ -321,6 +338,8 @@ struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
321338
if (!gpe || !gpdev)
322339
return NULL;
323340

341+
npe->table_group.ops = &pnv_pci_npu_ops;
342+
324343
list_for_each_entry(npdev, &pbus->devices, bus_list) {
325344
gptmp = pnv_pci_get_gpu_dev(npdev);
326345

@@ -333,6 +352,7 @@ struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
333352

334353
return gpe;
335354
}
355+
#endif /* !CONFIG_IOMMU_API */
336356

337357
/*
338358
* NPU2 ATS

‎arch/powerpc/platforms/powernv/pci-ioda.c

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2667,12 +2667,13 @@ static struct pnv_ioda_pe *gpe_table_group_to_npe(
26672667
static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
26682668
int num, struct iommu_table *tbl)
26692669
{
2670+
struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
26702671
long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
26712672

26722673
if (ret)
26732674
return ret;
26742675

2675-
ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2676+
ret = npe->table_group.ops->set_window(&npe->table_group, num, tbl);
26762677
if (ret)
26772678
pnv_pci_ioda2_unset_window(table_group, num);
26782679

@@ -2683,17 +2684,20 @@ static long pnv_pci_ioda2_npu_unset_window(
26832684
struct iommu_table_group *table_group,
26842685
int num)
26852686
{
2687+
struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
26862688
long ret = pnv_pci_ioda2_unset_window(table_group, num);
26872689

26882690
if (ret)
26892691
return ret;
26902692

2691-
return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2693+
return npe->table_group.ops->unset_window(&npe->table_group, num);
26922694
}
26932695

26942696
static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
26952697
{
2696-
pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2698+
struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2699+
2700+
npe->table_group.ops->take_ownership(&npe->table_group);
26972701
pnv_ioda2_take_ownership(table_group);
26982702
}
26992703

‎arch/powerpc/platforms/powernv/pci.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -214,11 +214,6 @@ extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
214214
extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
215215
extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
216216
extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
217-
extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
218-
struct iommu_table *tbl);
219-
extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
220-
extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
221-
extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
222217

223218
/* pci-ioda-tce.c */
224219
#define POWERNV_IOMMU_DEFAULT_LEVELS 1

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