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jpirkodavem330
jpirko
authored and
davem330
committed
mlxsw: pci: Allow to use CQEs of version 1 and version 2
Use previously added resources to query FW support for multiple versions of CQEs. Use the biggest version supported. For SDQs, it has no sense to use version 2 as it does not introduce any new features, but it is twice the size of CQE version 1. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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-11
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+91
-11
lines changed

‎drivers/net/ethernet/mellanox/mlxsw/cmd.h

Lines changed: 21 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -662,6 +662,12 @@ MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1);
662662
*/
663663
MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1);
664664

665+
/* cmd_mbox_config_set_cqe_version
666+
* Capability bit. Setting a bit to 1 configures the profile
667+
* according to the mailbox contents.
668+
*/
669+
MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1);
670+
665671
/* cmd_mbox_config_profile_max_vepa_channels
666672
* Maximum number of VEPA channels per port (0 through 16)
667673
* 0 - multi-channel VEPA is disabled
@@ -841,6 +847,14 @@ MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type,
841847
MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties,
842848
0x60, 0, 8, 0x08, 0x00, false);
843849

850+
/* cmd_mbox_config_profile_cqe_version
851+
* CQE version:
852+
* 0: CQE version is 0
853+
* 1: CQE version is either 1 or 2
854+
* CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver.
855+
*/
856+
MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8);
857+
844858
/* ACCESS_REG - Access EMAD Supported Register
845859
* ----------------------------------
846860
* OpMod == 0 (N/A), INMmod == 0 (N/A)
@@ -1032,11 +1046,15 @@ static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core,
10321046
0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE);
10331047
}
10341048

1035-
/* cmd_mbox_sw2hw_cq_cv
1049+
enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver {
1050+
MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1,
1051+
MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2,
1052+
};
1053+
1054+
/* cmd_mbox_sw2hw_cq_cqe_ver
10361055
* CQE Version.
1037-
* 0 - CQE Version 0, 1 - CQE Version 1
10381056
*/
1039-
MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cv, 0x00, 28, 4);
1057+
MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4);
10401058

10411059
/* cmd_mbox_sw2hw_cq_c_eqn
10421060
* Event Queue this CQ reports completion events to.

‎drivers/net/ethernet/mellanox/mlxsw/pci.c

Lines changed: 70 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,8 @@ struct mlxsw_pci {
156156
} cmd;
157157
struct mlxsw_bus_info bus_info;
158158
const struct pci_device_id *id;
159+
enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */
160+
u8 num_sdq_cqs; /* Number of CQs used for SDQs */
159161
};
160162

161163
static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
@@ -477,6 +479,17 @@ static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
477479
}
478480
}
479481

482+
static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci,
483+
struct mlxsw_pci_queue *q)
484+
{
485+
q->u.cq.v = mlxsw_pci->max_cqe_ver;
486+
487+
/* For SDQ it is pointless to use CQEv2, so use CQEv1 instead */
488+
if (q->u.cq.v == MLXSW_PCI_CQE_V2 &&
489+
q->num < mlxsw_pci->num_sdq_cqs)
490+
q->u.cq.v = MLXSW_PCI_CQE_V1;
491+
}
492+
480493
static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
481494
struct mlxsw_pci_queue *q)
482495
{
@@ -491,7 +504,13 @@ static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
491504
mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1);
492505
}
493506

494-
mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */
507+
if (q->u.cq.v == MLXSW_PCI_CQE_V1)
508+
mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
509+
MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1);
510+
else if (q->u.cq.v == MLXSW_PCI_CQE_V2)
511+
mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
512+
MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2);
513+
495514
mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
496515
mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
497516
mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
@@ -643,6 +662,18 @@ static void mlxsw_pci_cq_tasklet(unsigned long data)
643662
}
644663
}
645664

665+
static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q)
666+
{
667+
return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT :
668+
MLXSW_PCI_CQE01_COUNT;
669+
}
670+
671+
static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q)
672+
{
673+
return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE :
674+
MLXSW_PCI_CQE01_SIZE;
675+
}
676+
646677
static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
647678
struct mlxsw_pci_queue *q)
648679
{
@@ -755,11 +786,15 @@ static void mlxsw_pci_eq_tasklet(unsigned long data)
755786
struct mlxsw_pci_queue_ops {
756787
const char *name;
757788
enum mlxsw_pci_queue_type type;
789+
void (*pre_init)(struct mlxsw_pci *mlxsw_pci,
790+
struct mlxsw_pci_queue *q);
758791
int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
759792
struct mlxsw_pci_queue *q);
760793
void (*fini)(struct mlxsw_pci *mlxsw_pci,
761794
struct mlxsw_pci_queue *q);
762795
void (*tasklet)(unsigned long data);
796+
u16 (*elem_count_f)(const struct mlxsw_pci_queue *q);
797+
u8 (*elem_size_f)(const struct mlxsw_pci_queue *q);
763798
u16 elem_count;
764799
u8 elem_size;
765800
};
@@ -782,11 +817,12 @@ static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
782817

783818
static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
784819
.type = MLXSW_PCI_QUEUE_TYPE_CQ,
820+
.pre_init = mlxsw_pci_cq_pre_init,
785821
.init = mlxsw_pci_cq_init,
786822
.fini = mlxsw_pci_cq_fini,
787823
.tasklet = mlxsw_pci_cq_tasklet,
788-
.elem_count = MLXSW_PCI_CQE01_COUNT,
789-
.elem_size = MLXSW_PCI_CQE01_SIZE
824+
.elem_count_f = mlxsw_pci_cq_elem_count,
825+
.elem_size_f = mlxsw_pci_cq_elem_size
790826
};
791827

792828
static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
@@ -806,12 +842,15 @@ static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
806842
int i;
807843
int err;
808844

809-
q->u.cq.v = MLXSW_PCI_CQE_V0;
845+
q->num = q_num;
846+
if (q_ops->pre_init)
847+
q_ops->pre_init(mlxsw_pci, q);
810848

811849
spin_lock_init(&q->lock);
812-
q->num = q_num;
813-
q->count = q_ops->elem_count;
814-
q->elem_size = q_ops->elem_size;
850+
q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) :
851+
q_ops->elem_count;
852+
q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) :
853+
q_ops->elem_size;
815854
q->type = q_ops->type;
816855
q->pci = mlxsw_pci;
817856

@@ -840,7 +879,7 @@ static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
840879

841880
elem_info = mlxsw_pci_queue_elem_info_get(q, i);
842881
elem_info->elem =
843-
__mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i);
882+
__mlxsw_pci_queue_elem_get(q, q->elem_size, i);
844883
}
845884

846885
mlxsw_cmd_mbox_zero(mbox);
@@ -952,6 +991,8 @@ static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
952991
return -EINVAL;
953992
}
954993

994+
mlxsw_pci->num_sdq_cqs = num_sdqs;
995+
955996
err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
956997
num_eqs);
957998
if (err) {
@@ -1192,6 +1233,11 @@ static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
11921233
mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
11931234
&profile->swid_config[i]);
11941235

1236+
if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) {
1237+
mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);
1238+
mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
1239+
}
1240+
11951241
return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
11961242
}
11971243

@@ -1386,6 +1432,21 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
13861432
if (err)
13871433
goto err_query_resources;
13881434

1435+
if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) &&
1436+
MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2))
1437+
mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2;
1438+
else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) &&
1439+
MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1))
1440+
mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1;
1441+
else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) &&
1442+
MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) ||
1443+
!MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) {
1444+
mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0;
1445+
} else {
1446+
dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n");
1447+
goto err_cqe_v_check;
1448+
}
1449+
13891450
err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
13901451
if (err)
13911452
goto err_config_profile;
@@ -1408,6 +1469,7 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
14081469
mlxsw_pci_aqs_fini(mlxsw_pci);
14091470
err_aqs_init:
14101471
err_config_profile:
1472+
err_cqe_v_check:
14111473
err_query_resources:
14121474
err_boardinfo:
14131475
mlxsw_pci_fw_area_fini(mlxsw_pci);

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