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llandwerlin-inteltursulin
llandwerlin-intel
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tursulin
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drm/i915: Record the sseu configuration per-context & engine
We want to expose the ability to reconfigure the slices, subslice and eu per context and per engine. To facilitate that, store the current configuration on the context for each engine, which is initially set to the device default upon creation. v2: record sseu configuration per context & engine (Chris) v3: introduce the i915_gem_context_sseu to store powergating programming, sseu_dev_info has grown quite a bit (Lionel) v4: rename i915_gem_sseu into intel_sseu (Chris) use to_intel_context() (Chris) v5: More to_intel_context() (Tvrtko) Switch intel_sseu from union to struct (Tvrtko) Move context default sseu in existing loop (Chris) v6: s/intel_sseu_from_device_sseu/intel_device_default_sseu/ (Tvrtko) Tvrtko Ursulin: v7: * Pass intel_sseu by pointer instead of value to make_rpcs. * Rebase for make_rpcs changes. v8: * Rebase for RPCS edit on pin. v9: * Rebase for context image setup changes. v10: * Rename dev_priv to i915. (Chris Wilson) v11: * Rebase. v12: * Rebase for IS_GEN changes. v13: * Rebase for RUNTIME_INFO. v14: * Rebase for intel_context_init. v15: * Rebase for drm-tip changes. v16: * Moved struct intel_sseu definition to i915_gem_context.h. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190205095032.22673-1-tvrtko.ursulin@linux.intel.com
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+47
-15
lines changed

4 files changed

+47
-15
lines changed

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3305,6 +3305,20 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
33053305
return (struct intel_device_info *)INTEL_INFO(dev_priv);
33063306
}
33073307

3308+
static inline struct intel_sseu
3309+
intel_device_default_sseu(struct drm_i915_private *i915)
3310+
{
3311+
const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
3312+
struct intel_sseu value = {
3313+
.slice_mask = sseu->slice_mask,
3314+
.subslice_mask = sseu->subslice_mask[0],
3315+
.min_eus_per_subslice = sseu->max_eus_per_subslice,
3316+
.max_eus_per_subslice = sseu->max_eus_per_subslice,
3317+
};
3318+
3319+
return value;
3320+
}
3321+
33083322
/* modesetting */
33093323
extern void intel_modeset_init_hw(struct drm_device *dev);
33103324
extern int intel_modeset_init(struct drm_device *dev);

‎drivers/gpu/drm/i915/i915_gem_context.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -330,6 +330,9 @@ intel_context_init(struct intel_context *ce,
330330

331331
INIT_LIST_HEAD(&ce->signal_link);
332332
INIT_LIST_HEAD(&ce->signals);
333+
334+
/* Use the whole device by default */
335+
ce->sseu = intel_device_default_sseu(ctx->i915);
333336
}
334337

335338
static struct i915_gem_context *

‎drivers/gpu/drm/i915/i915_gem_context.h

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131

3232
#include "i915_gem.h"
3333
#include "i915_scheduler.h"
34+
#include "intel_device_info.h"
3435

3536
struct pid;
3637

@@ -53,6 +54,16 @@ struct intel_context_ops {
5354
void (*destroy)(struct intel_context *ce);
5455
};
5556

57+
/*
58+
* Powergating configuration for a particular (context,engine).
59+
*/
60+
struct intel_sseu {
61+
u8 slice_mask;
62+
u8 subslice_mask;
63+
u8 min_eus_per_subslice;
64+
u8 max_eus_per_subslice;
65+
};
66+
5667
/**
5768
* struct i915_gem_context - client state
5869
*
@@ -173,6 +184,9 @@ struct i915_gem_context {
173184
int pin_count;
174185

175186
const struct intel_context_ops *ops;
187+
188+
/** sseu: Control eu/slice partitioning */
189+
struct intel_sseu sseu;
176190
} __engine[I915_NUM_ENGINES];
177191

178192
/** ring_size: size for allocating the per-engine ring buffer */

‎drivers/gpu/drm/i915/intel_lrc.c

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1266,7 +1266,8 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
12661266
return i915_vma_pin(vma, 0, 0, flags);
12671267
}
12681268

1269-
static u32 make_rpcs(struct drm_i915_private *dev_priv);
1269+
static u32
1270+
make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu);
12701271

12711272
static void
12721273
__execlists_update_reg_state(struct intel_engine_cs *engine,
@@ -1281,7 +1282,8 @@ __execlists_update_reg_state(struct intel_engine_cs *engine,
12811282

12821283
/* RPCS */
12831284
if (engine->class == RENDER_CLASS)
1284-
regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915);
1285+
regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915,
1286+
&ce->sseu);
12851287
}
12861288

12871289
static struct intel_context *
@@ -2432,18 +2434,19 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
24322434
}
24332435

24342436
static u32
2435-
make_rpcs(struct drm_i915_private *dev_priv)
2437+
make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu)
24362438
{
2437-
bool subslice_pg = RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg;
2438-
u8 slices = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
2439-
u8 subslices = hweight8(RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0]);
2439+
const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
2440+
bool subslice_pg = sseu->has_subslice_pg;
2441+
u8 slices = hweight8(ctx_sseu->slice_mask);
2442+
u8 subslices = hweight8(ctx_sseu->subslice_mask);
24402443
u32 rpcs = 0;
24412444

24422445
/*
24432446
* No explicit RPCS request is needed to ensure full
24442447
* slice/subslice/EU enablement prior to Gen9.
24452448
*/
2446-
if (INTEL_GEN(dev_priv) < 9)
2449+
if (INTEL_GEN(i915) < 9)
24472450
return 0;
24482451

24492452
/*
@@ -2471,7 +2474,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
24712474
* subslices are enabled, or a count between one and four on the first
24722475
* slice.
24732476
*/
2474-
if (IS_GEN(dev_priv, 11) && slices == 1 && subslices >= 4) {
2477+
if (IS_GEN(i915, 11) && slices == 1 && subslices >= 4) {
24752478
GEM_BUG_ON(subslices & 1);
24762479

24772480
subslice_pg = false;
@@ -2484,10 +2487,10 @@ make_rpcs(struct drm_i915_private *dev_priv)
24842487
* must make an explicit request through RPCS for full
24852488
* enablement.
24862489
*/
2487-
if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) {
2490+
if (sseu->has_slice_pg) {
24882491
u32 mask, val = slices;
24892492

2490-
if (INTEL_GEN(dev_priv) >= 11) {
2493+
if (INTEL_GEN(i915) >= 11) {
24912494
mask = GEN11_RPCS_S_CNT_MASK;
24922495
val <<= GEN11_RPCS_S_CNT_SHIFT;
24932496
} else {
@@ -2512,18 +2515,16 @@ make_rpcs(struct drm_i915_private *dev_priv)
25122515
rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
25132516
}
25142517

2515-
if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) {
2518+
if (sseu->has_eu_pg) {
25162519
u32 val;
25172520

2518-
val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice <<
2519-
GEN8_RPCS_EU_MIN_SHIFT;
2521+
val = ctx_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
25202522
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
25212523
val &= GEN8_RPCS_EU_MIN_MASK;
25222524

25232525
rpcs |= val;
25242526

2525-
val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice <<
2526-
GEN8_RPCS_EU_MAX_SHIFT;
2527+
val = ctx_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;
25272528
GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
25282529
val &= GEN8_RPCS_EU_MAX_MASK;
25292530

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