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Javier Martinez CanillasKukjin Kim
Javier Martinez Canillas
authored and
Kukjin Kim
committed
clk: exynos5420: Add IDs for clocks used in DISP1 power domain
When a power domain is powered off on Exynos5420 SoC, the input clocks of the devices attached to this power domain are re-parented to oscclk and restored to the original parent after powering on the power domain. So a reference to the input and parent clocks for the devices attached to a power domain are needed to be able to do the re-parenting. The DISP1 pd includes modules which uses the following clocks: ACLK_200_DISP1 (MIXER and HDMILINK) ACLK_300_DISP1 (FIMD1) ACLK_400_DISP1 (Internal Buses) Each of these clocks are generated as the output of a clock mux so add an ID for all of these clock muxes and their parents to be referenced in the DISP1 power domain device node. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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‎drivers/clk/samsung/clk-exynos5420.c

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -635,8 +635,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
635635
SRC_TOP3, 0, 1),
636636
MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
637637
SRC_TOP3, 4, 1),
638-
MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
639-
SRC_TOP3, 8, 1),
638+
MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
639+
mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
640640
MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
641641
SRC_TOP3, 12, 1),
642642
MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
@@ -663,8 +663,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
663663
MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
664664
SRC_TOP4, 28, 1),
665665

666-
MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
667-
SRC_TOP5, 0, 1),
666+
MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
667+
mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
668668
MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
669669
SRC_TOP5, 4, 1),
670670
MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
@@ -675,8 +675,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
675675
SRC_TOP5, 16, 1),
676676
MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
677677
SRC_TOP5, 20, 1),
678-
MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
679-
SRC_TOP5, 24, 1),
678+
MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
679+
mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
680680
MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
681681
SRC_TOP5, 28, 1),
682682

@@ -693,7 +693,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
693693
SRC_TOP10, 0, 1),
694694
MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
695695
SRC_TOP10, 4, 1),
696-
MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
696+
MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
697+
SRC_TOP10, 8, 1),
697698
MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
698699
SRC_TOP10, 12, 1),
699700
MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
@@ -717,17 +718,17 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
717718
MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
718719
SRC_TOP11, 28, 1),
719720

720-
MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
721-
SRC_TOP12, 4, 1),
721+
MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
722+
mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
722723
MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
723724
SRC_TOP12, 8, 1),
724725
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
725726
SRC_TOP12, 12, 1),
726727
MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
727728
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
728729
SRC_TOP12, 20, 1),
729-
MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
730-
SRC_TOP12, 24, 1),
730+
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
731+
mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
731732
MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
732733
SRC_TOP12, 28, 1),
733734

‎include/dt-bindings/clock/exynos5420.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,12 @@
204204
#define CLK_MOUT_MAUDIO0 643
205205
#define CLK_MOUT_USER_ACLK333 644
206206
#define CLK_MOUT_SW_ACLK333 645
207+
#define CLK_MOUT_USER_ACLK200_DISP1 646
208+
#define CLK_MOUT_SW_ACLK200 647
209+
#define CLK_MOUT_USER_ACLK300_DISP1 648
210+
#define CLK_MOUT_SW_ACLK300 649
211+
#define CLK_MOUT_USER_ACLK400_DISP1 650
212+
#define CLK_MOUT_SW_ACLK400 651
207213

208214
/* divider clocks */
209215
#define CLK_DOUT_PIXEL 768

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