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torvaldstorvalds
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Merge tag 'armsoc-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "Another week, another small batch of fixes. Most of these make zynq, socfpga and sunxi platforms work a bit better: - due to new requirements for regulators, DWMMC on socfpga broke past v3.17 - SMP spinup fix for socfpga - a few DT fixes for zynq - another option (FIXED_REGULATOR) for sunxi is needed that used to be selected by other options but no longer is. - a couple of small DT fixes for at91 - ...and a couple for i.MX" * tag 'armsoc-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: dts: imx28-evk: Let i2c0 run at 100kHz ARM: i.MX6: Fix "emi" clock name typo ARM: multi_v7_defconfig: enable CONFIG_MMC_DW_ROCKCHIP ARM: sunxi_defconfig: enable CONFIG_REGULATOR_FIXED_VOLTAGE ARM: dts: socfpga: Add a 3.3V fixed regulator node ARM: dts: socfpga: Fix SD card detect ARM: dts: socfpga: rename gpio nodes ARM: at91/dt: sam9263: fix PLLB frequencies power: reset: at91-reset: fix power down register MAINTAINERS: add atmel ssc driver maintainer entry arm: socfpga: fix fetching cpu1start_addr for SMP ARM: zynq: DT: trivial: Fix mc node ARM: zynq: DT: Add cadence watchdog node ARM: zynq: DT: Add missing reference for memory-controller ARM: zynq: DT: Add missing reference for ADC ARM: zynq: DT: Add missing address for L2 pl310 ARM: zynq: DT: Remove 222 MHz OPP ARM: zynq: DT: Fix GEM register area size
2 parents d1e14f1 + efc176a commit 88e2376

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18 files changed

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‎MAINTAINERS

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1749,6 +1749,13 @@ M: Nicolas Ferre <nicolas.ferre@atmel.com>
17491749
S: Supported
17501750
F: drivers/spi/spi-atmel.*
17511751

1752+
ATMEL SSC DRIVER
1753+
M: Bo Shen <voice.shen@atmel.com>
1754+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1755+
S: Supported
1756+
F: drivers/misc/atmel-ssc.c
1757+
F: include/linux/atmel-ssc.h
1758+
17521759
ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS
17531760
M: Nicolas Ferre <nicolas.ferre@atmel.com>
17541761
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

‎arch/arm/boot/dts/at91sam9263.dtsi

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -122,9 +122,10 @@
122122
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
123123
clocks = <&main>;
124124
reg = <1>;
125-
atmel,clk-input-range = <1000000 5000000>;
125+
atmel,clk-input-range = <1000000 32000000>;
126126
#atmel,pll-clk-output-range-cells = <4>;
127-
atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
127+
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
128+
<190000000 240000000 2 1>;
128129
};
129130

130131
mck: masterck {

‎arch/arm/boot/dts/imx28-evk.dts

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,6 @@
193193
i2c0: i2c@80058000 {
194194
pinctrl-names = "default";
195195
pinctrl-0 = <&i2c0_pins_a>;
196-
clock-frequency = <400000>;
197196
status = "okay";
198197

199198
sgtl5000: codec@0a {

‎arch/arm/boot/dts/socfpga.dtsi

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -547,15 +547,15 @@
547547
status = "disabled";
548548
};
549549

550-
gpio@ff708000 {
550+
gpio0: gpio@ff708000 {
551551
#address-cells = <1>;
552552
#size-cells = <0>;
553553
compatible = "snps,dw-apb-gpio";
554554
reg = <0xff708000 0x1000>;
555555
clocks = <&per_base_clk>;
556556
status = "disabled";
557557

558-
gpio0: gpio-controller@0 {
558+
porta: gpio-controller@0 {
559559
compatible = "snps,dw-apb-gpio-port";
560560
gpio-controller;
561561
#gpio-cells = <2>;
@@ -567,15 +567,15 @@
567567
};
568568
};
569569

570-
gpio@ff709000 {
570+
gpio1: gpio@ff709000 {
571571
#address-cells = <1>;
572572
#size-cells = <0>;
573573
compatible = "snps,dw-apb-gpio";
574574
reg = <0xff709000 0x1000>;
575575
clocks = <&per_base_clk>;
576576
status = "disabled";
577577

578-
gpio1: gpio-controller@0 {
578+
portb: gpio-controller@0 {
579579
compatible = "snps,dw-apb-gpio-port";
580580
gpio-controller;
581581
#gpio-cells = <2>;
@@ -587,15 +587,15 @@
587587
};
588588
};
589589

590-
gpio@ff70a000 {
590+
gpio2: gpio@ff70a000 {
591591
#address-cells = <1>;
592592
#size-cells = <0>;
593593
compatible = "snps,dw-apb-gpio";
594594
reg = <0xff70a000 0x1000>;
595595
clocks = <&per_base_clk>;
596596
status = "disabled";
597597

598-
gpio2: gpio-controller@0 {
598+
portc: gpio-controller@0 {
599599
compatible = "snps,dw-apb-gpio-port";
600600
gpio-controller;
601601
#gpio-cells = <2>;

‎arch/arm/boot/dts/socfpga_arria5.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
};
3030
};
3131

32-
dwmmc0@ff704000 {
32+
mmc0: dwmmc0@ff704000 {
3333
num-slots = <1>;
3434
broken-cd;
3535
bus-width = <4>;

‎arch/arm/boot/dts/socfpga_arria5_socdk.dts

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,13 @@
3737
*/
3838
ethernet0 = &gmac1;
3939
};
40+
41+
regulator_3_3v: 3-3-v-regulator {
42+
compatible = "regulator-fixed";
43+
regulator-name = "3.3V";
44+
regulator-min-microvolt = <3300000>;
45+
regulator-max-microvolt = <3300000>;
46+
};
4047
};
4148

4249
&gmac1 {
@@ -68,6 +75,11 @@
6875
};
6976
};
7077

78+
&mmc0 {
79+
vmmc-supply = <&regulator_3_3v>;
80+
vqmmc-supply = <&regulator_3_3v>;
81+
};
82+
7183
&usb1 {
7284
status = "okay";
7385
};

‎arch/arm/boot/dts/socfpga_cyclone5_socdk.dts

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,13 @@
3737
*/
3838
ethernet0 = &gmac1;
3939
};
40+
41+
regulator_3_3v: 3-3-v-regulator {
42+
compatible = "regulator-fixed";
43+
regulator-name = "3.3V";
44+
regulator-min-microvolt = <3300000>;
45+
regulator-max-microvolt = <3300000>;
46+
};
4047
};
4148

4249
&gmac1 {
@@ -53,6 +60,10 @@
5360
rxc-skew-ps = <2000>;
5461
};
5562

63+
&gpio1 {
64+
status = "okay";
65+
};
66+
5667
&i2c0 {
5768
status = "okay";
5869

@@ -69,7 +80,9 @@
6980
};
7081

7182
&mmc0 {
72-
cd-gpios = <&gpio1 18 0>;
83+
cd-gpios = <&portb 18 0>;
84+
vmmc-supply = <&regulator_3_3v>;
85+
vqmmc-supply = <&regulator_3_3v>;
7386
};
7487

7588
&usb1 {

‎arch/arm/boot/dts/socfpga_cyclone5_sockit.dts

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,13 @@
3737
*/
3838
ethernet0 = &gmac1;
3939
};
40+
41+
regulator_3_3v: vcc3p3-regulator {
42+
compatible = "regulator-fixed";
43+
regulator-name = "VCC3P3";
44+
regulator-min-microvolt = <3300000>;
45+
regulator-max-microvolt = <3300000>;
46+
};
4047
};
4148

4249
&gmac1 {
@@ -53,6 +60,11 @@
5360
rxc-skew-ps = <2000>;
5461
};
5562

63+
&mmc0 {
64+
vmmc-supply = <&regulator_3_3v>;
65+
vqmmc-supply = <&regulator_3_3v>;
66+
};
67+
5668
&usb1 {
5769
status = "okay";
5870
};

‎arch/arm/boot/dts/zynq-7000.dtsi

Lines changed: 17 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,6 @@
3030
/* kHz uV */
3131
666667 1000000
3232
333334 1000000
33-
222223 1000000
3433
>;
3534
};
3635

@@ -65,7 +64,7 @@
6564
interrupt-parent = <&intc>;
6665
ranges;
6766

68-
adc@f8007100 {
67+
adc: adc@f8007100 {
6968
compatible = "xlnx,zynq-xadc-1.00.a";
7069
reg = <0xf8007100 0x20>;
7170
interrupts = <0 7 4>;
@@ -137,7 +136,7 @@
137136
<0xF8F00100 0x100>;
138137
};
139138

140-
L2: cache-controller {
139+
L2: cache-controller@f8f02000 {
141140
compatible = "arm,pl310-cache";
142141
reg = <0xF8F02000 0x1000>;
143142
arm,data-latency = <3 2 2>;
@@ -146,10 +145,10 @@
146145
cache-level = <2>;
147146
};
148147

149-
memory-controller@f8006000 {
148+
mc: memory-controller@f8006000 {
150149
compatible = "xlnx,zynq-ddrc-a05";
151150
reg = <0xf8006000 0x1000>;
152-
} ;
151+
};
153152

154153
uart0: serial@e0000000 {
155154
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
@@ -195,7 +194,7 @@
195194

196195
gem0: ethernet@e000b000 {
197196
compatible = "cdns,gem";
198-
reg = <0xe000b000 0x4000>;
197+
reg = <0xe000b000 0x1000>;
199198
status = "disabled";
200199
interrupts = <0 22 4>;
201200
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
@@ -206,7 +205,7 @@
206205

207206
gem1: ethernet@e000c000 {
208207
compatible = "cdns,gem";
209-
reg = <0xe000c000 0x4000>;
208+
reg = <0xe000c000 0x1000>;
210209
status = "disabled";
211210
interrupts = <0 45 4>;
212211
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
@@ -315,5 +314,16 @@
315314
reg = <0xf8f00600 0x20>;
316315
clocks = <&clkc 4>;
317316
};
317+
318+
watchdog0: watchdog@f8005000 {
319+
clocks = <&clkc 45>;
320+
compatible = "xlnx,zynq-wdt-r1p2";
321+
device_type = "watchdog";
322+
interrupt-parent = <&intc>;
323+
interrupts = <0 9 1>;
324+
reg = <0xf8005000 0x1000>;
325+
reset = <0>;
326+
timeout-sec = <10>;
327+
};
318328
};
319329
};

‎arch/arm/configs/multi_v7_defconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -354,6 +354,7 @@ CONFIG_MMC_MVSDIO=y
354354
CONFIG_MMC_SUNXI=y
355355
CONFIG_MMC_DW=y
356356
CONFIG_MMC_DW_EXYNOS=y
357+
CONFIG_MMC_DW_ROCKCHIP=y
357358
CONFIG_NEW_LEDS=y
358359
CONFIG_LEDS_CLASS=y
359360
CONFIG_LEDS_GPIO=y

‎arch/arm/configs/sunxi_defconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ CONFIG_WATCHDOG=y
7676
CONFIG_SUNXI_WATCHDOG=y
7777
CONFIG_MFD_AXP20X=y
7878
CONFIG_REGULATOR=y
79+
CONFIG_REGULATOR_FIXED_VOLTAGE=y
7980
CONFIG_REGULATOR_GPIO=y
8081
CONFIG_USB=y
8182
CONFIG_USB_EHCI_HCD=y

‎arch/arm/mach-imx/clk-imx6q.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,8 @@ static const char *pcie_axi_sels[] = { "axi", "ahb", };
5050
static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
5151
static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
5252
static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
53-
static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
54-
static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
53+
static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
54+
static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
5555
static const char *vdo_axi_sels[] = { "axi", "ahb", };
5656
static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
5757
static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
@@ -302,8 +302,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
302302
clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
303303
clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
304304
clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
305-
clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
306-
clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
305+
clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
306+
clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
307307
clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
308308
clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
309309
clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
@@ -354,8 +354,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
354354
clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
355355
clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
356356
clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
357-
clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
358-
clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
357+
clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
358+
clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
359359
clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
360360
clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
361361
clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
@@ -456,7 +456,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
456456
clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
457457
clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
458458
clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
459-
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
459+
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
460460
clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
461461
clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
462462
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);

‎arch/arm/mach-socfpga/core.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ extern void __iomem *rst_manager_base_addr;
4040
extern struct smp_operations socfpga_smp_ops;
4141
extern char secondary_trampoline, secondary_trampoline_end;
4242

43-
extern unsigned long cpu1start_addr;
43+
extern unsigned long socfpga_cpu1start_addr;
4444

4545
#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
4646

‎arch/arm/mach-socfpga/headsmp.S

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,21 +9,26 @@
99
*/
1010
#include <linux/linkage.h>
1111
#include <linux/init.h>
12+
#include <asm/memory.h>
1213

1314
.arch armv7-a
1415

1516
ENTRY(secondary_trampoline)
16-
movw r2, #:lower16:cpu1start_addr
17-
movt r2, #:upper16:cpu1start_addr
18-
19-
/* The socfpga VT cannot handle a 0xC0000000 page offset when loading
20-
the cpu1start_addr, we bit clear it. Tested on HW and VT. */
21-
bic r2, r2, #0x40000000
22-
23-
ldr r0, [r2]
24-
ldr r1, [r0]
25-
bx r1
17+
/* CPU1 will always fetch from 0x0 when it is brought out of reset.
18+
* Thus, we can just subtract the PAGE_OFFSET to get the physical
19+
* address of &cpu1start_addr. This would not work for platforms
20+
* where the physical memory does not start at 0x0.
21+
*/
22+
adr r0, 1f
23+
ldmia r0, {r1, r2}
24+
sub r2, r2, #PAGE_OFFSET
25+
ldr r3, [r2]
26+
ldr r4, [r3]
27+
bx r4
2628

29+
.align
30+
1: .long .
31+
.long socfpga_cpu1start_addr
2732
ENTRY(secondary_trampoline_end)
2833

2934
ENTRY(socfpga_secondary_startup)

‎arch/arm/mach-socfpga/platsmp.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,11 +33,11 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
3333
{
3434
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
3535

36-
if (cpu1start_addr) {
36+
if (socfpga_cpu1start_addr) {
3737
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
3838

3939
__raw_writel(virt_to_phys(socfpga_secondary_startup),
40-
(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
40+
(sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)));
4141

4242
flush_cache_all();
4343
smp_wmb();

‎arch/arm/mach-socfpga/socfpga.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
3030
void __iomem *sys_manager_base_addr;
3131
void __iomem *rst_manager_base_addr;
32-
unsigned long cpu1start_addr;
32+
unsigned long socfpga_cpu1start_addr;
3333

3434
static struct map_desc scu_io_desc __initdata = {
3535
.virtual = SOCFPGA_SCU_VIRT_BASE,
@@ -70,7 +70,7 @@ void __init socfpga_sysmgr_init(void)
7070
np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
7171

7272
if (of_property_read_u32(np, "cpu1-start-addr",
73-
(u32 *) &cpu1start_addr))
73+
(u32 *) &socfpga_cpu1start_addr))
7474
pr_err("SMP: Need cpu1-start-addr in device tree.\n");
7575

7676
sys_manager_base_addr = of_iomap(np, 0);

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