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Cyrille Pitchenherbertx
Cyrille Pitchen
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herbertx
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crypto: atmel-authenc - add support to authenc(hmac(shaX), Y(aes)) modes
This patchs allows to combine the AES and SHA hardware accelerators on some Atmel SoCs. Doing so, AES blocks are only written to/read from the AES hardware. Those blocks are also transferred from the AES to the SHA accelerator internally, without additionnal accesses to the system busses. Hence, the AES and SHA accelerators work in parallel to process all the data blocks, instead of serializing the process by (de)crypting those blocks first then authenticating them after like the generic crypto/authenc.c driver does. Of course, both the AES and SHA hardware accelerators need to be available before we can start to process the data blocks. Hence we use their crypto request queue to synchronize both drivers. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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‎drivers/crypto/Kconfig

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@@ -415,6 +415,18 @@ config CRYPTO_DEV_BFIN_CRC
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Newer Blackfin processors have CRC hardware. Select this if you
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want to use the Blackfin CRC module.
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config CRYPTO_DEV_ATMEL_AUTHENC
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tristate "Support for Atmel IPSEC/SSL hw accelerator"
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depends on (ARCH_AT91 && HAS_DMA) || COMPILE_TEST
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select CRYPTO_AUTHENC
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select CRYPTO_DEV_ATMEL_AES
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select CRYPTO_DEV_ATMEL_SHA
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help
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Some Atmel processors can combine the AES and SHA hw accelerators
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to enhance support of IPSEC/SSL.
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Select this if you want to use the Atmel modules for
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authenc(hmac(shaX),Y(cbc)) algorithms.
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config CRYPTO_DEV_ATMEL_AES
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tristate "Support for Atmel AES hw accelerator"
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depends on HAS_DMA

‎drivers/crypto/atmel-aes-regs.h

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@@ -68,6 +68,22 @@
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#define AES_CTRR 0x98
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#define AES_GCMHR(x) (0x9c + ((x) * 0x04))
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#define AES_EMR 0xb0
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#define AES_EMR_APEN BIT(0) /* Auto Padding Enable */
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#define AES_EMR_APM BIT(1) /* Auto Padding Mode */
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#define AES_EMR_APM_IPSEC 0x0
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#define AES_EMR_APM_SSL BIT(1)
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#define AES_EMR_PLIPEN BIT(4) /* PLIP Enable */
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#define AES_EMR_PLIPD BIT(5) /* PLIP Decipher */
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#define AES_EMR_PADLEN_MASK (0xFu << 8)
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#define AES_EMR_PADLEN_OFFSET 8
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#define AES_EMR_PADLEN(padlen) (((padlen) << AES_EMR_PADLEN_OFFSET) &\
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AES_EMR_PADLEN_MASK)
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#define AES_EMR_NHEAD_MASK (0xFu << 16)
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#define AES_EMR_NHEAD_OFFSET 16
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#define AES_EMR_NHEAD(nhead) (((nhead) << AES_EMR_NHEAD_OFFSET) &\
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AES_EMR_NHEAD_MASK)
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#define AES_TWR(x) (0xc0 + ((x) * 0x04))
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#define AES_ALPHAR(x) (0xd0 + ((x) * 0x04))
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