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Merge git://linux-arm.org/linux-ld into drm-next
Pull upstream HDLCD driver. * git://linux-arm.org/linux-ld: MAINTAINERS: Add Liviu Dudau as maintainer for ARM HDLCD driver. drm: Add support for ARM's HDLCD controller.
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‎MAINTAINERS

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@@ -827,6 +827,12 @@ S: Maintained
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F: drivers/net/arcnet/
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F: include/uapi/linux/if_arcnet.h
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ARM HDLCD DRM DRIVER
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M: Liviu Dudau <liviu.dudau@arm.com>
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S: Supported
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F: drivers/gpu/drm/arm/
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F: Documentation/devicetree/bindings/display/arm,hdlcd.txt
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ARM MFM AND FLOPPY DRIVERS
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M: Ian Molton <spyro@f2s.com>
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S: Maintained

‎drivers/gpu/drm/Kconfig

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@@ -106,6 +106,8 @@ config DRM_TDFX
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Choose this option if you have a 3dfx Banshee or Voodoo3 (or later),
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graphics card. If M is selected, the module will be called tdfx.
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source "drivers/gpu/drm/arm/Kconfig"
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config DRM_R128
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tristate "ATI Rage 128"
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depends on DRM && PCI

‎drivers/gpu/drm/Makefile

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@@ -33,6 +33,7 @@ CFLAGS_drm_trace_points.o := -I$(src)
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obj-$(CONFIG_DRM) += drm.o
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obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
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obj-$(CONFIG_DRM_ARM) += arm/
3637
obj-$(CONFIG_DRM_TTM) += ttm/
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obj-$(CONFIG_DRM_TDFX) += tdfx/
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obj-$(CONFIG_DRM_R128) += r128/

‎drivers/gpu/drm/arm/Kconfig

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@@ -0,0 +1,27 @@
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config DRM_ARM
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bool
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help
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Choose this option to select drivers for ARM's devices
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config DRM_HDLCD
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tristate "ARM HDLCD"
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depends on DRM && OF && (ARM || ARM64)
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depends on COMMON_CLK
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select DRM_ARM
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select DRM_KMS_HELPER
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select DRM_KMS_FB_HELPER
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select DRM_KMS_CMA_HELPER
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help
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Choose this option if you have an ARM High Definition Colour LCD
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controller.
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If M is selected the module will be called hdlcd.
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config DRM_HDLCD_SHOW_UNDERRUN
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bool "Show underrun conditions"
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depends on DRM_HDLCD
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default n
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help
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Enable this option to show in red colour the pixels that the
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HDLCD device did not fetch from framebuffer due to underrun
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conditions.

‎drivers/gpu/drm/arm/Makefile

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@@ -0,0 +1,2 @@
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hdlcd-y := hdlcd_drv.o hdlcd_crtc.o
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obj-$(CONFIG_DRM_HDLCD) += hdlcd.o

‎drivers/gpu/drm/arm/hdlcd_crtc.c

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/*
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* Copyright (C) 2013-2015 ARM Limited
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*
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* Implementation of a CRTC class for the HDLCD driver.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_of.h>
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#include <drm/drm_plane_helper.h>
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#include <linux/clk.h>
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#include <linux/of_graph.h>
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#include <linux/platform_data/simplefb.h>
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#include <video/videomode.h>
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#include "hdlcd_drv.h"
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#include "hdlcd_regs.h"
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/*
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* The HDLCD controller is a dumb RGB streamer that gets connected to
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* a single HDMI transmitter or in the case of the ARM Models it gets
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* emulated by the software that does the actual rendering.
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*
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*/
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static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
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.destroy = drm_crtc_cleanup,
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.set_config = drm_atomic_helper_set_config,
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.page_flip = drm_atomic_helper_page_flip,
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.reset = drm_atomic_helper_crtc_reset,
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
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};
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static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;
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/*
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* Setup the HDLCD registers for decoding the pixels out of the framebuffer
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*/
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static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
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{
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unsigned int btpp;
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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uint32_t pixel_format;
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struct simplefb_format *format = NULL;
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int i;
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pixel_format = crtc->primary->state->fb->pixel_format;
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for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
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if (supported_formats[i].fourcc == pixel_format)
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format = &supported_formats[i];
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}
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if (WARN_ON(!format))
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return 0;
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/* HDLCD uses 'bytes per pixel', zero means 1 byte */
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btpp = (format->bits_per_pixel + 7) / 8;
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hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
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/*
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* The format of the HDLCD_REG_<color>_SELECT register is:
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* - bits[23:16] - default value for that color component
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* - bits[11:8] - number of bits to extract for each color component
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* - bits[4:0] - index of the lowest bit to extract
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*
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* The default color value is used when bits[11:8] are zero, when the
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* pixel is outside the visible frame area or when there is a
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* buffer underrun.
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*/
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hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
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#ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
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0x00ff0000 | /* show underruns in red */
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#endif
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((format->red.length & 0xf) << 8));
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hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
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((format->green.length & 0xf) << 8));
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hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
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((format->blue.length & 0xf) << 8));
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return 0;
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}
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static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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struct drm_display_mode *m = &crtc->state->adjusted_mode;
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struct videomode vm;
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unsigned int polarities, line_length, err;
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vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
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vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
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vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
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vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
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vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
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vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
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polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;
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if (m->flags & DRM_MODE_FLAG_PHSYNC)
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polarities |= HDLCD_POLARITY_HSYNC;
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if (m->flags & DRM_MODE_FLAG_PVSYNC)
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polarities |= HDLCD_POLARITY_VSYNC;
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line_length = crtc->primary->state->fb->pitches[0];
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/* Allow max number of outstanding requests and largest burst size */
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hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
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HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);
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hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, line_length);
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hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, line_length);
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hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, m->crtc_vdisplay - 1);
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hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
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hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
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hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
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hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
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hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
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hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
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hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
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hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
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hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
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err = hdlcd_set_pxl_fmt(crtc);
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if (err)
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return;
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clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
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}
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static void hdlcd_crtc_enable(struct drm_crtc *crtc)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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clk_prepare_enable(hdlcd->clk);
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
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drm_crtc_vblank_on(crtc);
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}
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static void hdlcd_crtc_disable(struct drm_crtc *crtc)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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if (!crtc->primary->fb)
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return;
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clk_disable_unprepare(hdlcd->clk);
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
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drm_crtc_vblank_off(crtc);
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}
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static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
165+
{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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struct drm_display_mode *mode = &state->adjusted_mode;
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long rate, clk_rate = mode->clock * 1000;
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rate = clk_round_rate(hdlcd->clk, clk_rate);
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if (rate != clk_rate) {
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/* clock required by mode not supported by hardware */
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return -EINVAL;
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}
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return 0;
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}
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static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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unsigned long flags;
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if (crtc->state->event) {
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struct drm_pending_vblank_event *event = crtc->state->event;
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crtc->state->event = NULL;
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event->pipe = drm_crtc_index(crtc);
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WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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list_add_tail(&event->base.link, &hdlcd->event_list);
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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}
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}
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static void hdlcd_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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}
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static bool hdlcd_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
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.mode_fixup = hdlcd_crtc_mode_fixup,
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.mode_set = drm_helper_crtc_mode_set,
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.mode_set_base = drm_helper_crtc_mode_set_base,
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.mode_set_nofb = hdlcd_crtc_mode_set_nofb,
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.enable = hdlcd_crtc_enable,
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.disable = hdlcd_crtc_disable,
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.prepare = hdlcd_crtc_disable,
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.commit = hdlcd_crtc_enable,
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.atomic_check = hdlcd_crtc_atomic_check,
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.atomic_begin = hdlcd_crtc_atomic_begin,
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.atomic_flush = hdlcd_crtc_atomic_flush,
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};
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static int hdlcd_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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return 0;
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}
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static void hdlcd_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct hdlcd_drm_private *hdlcd;
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struct drm_gem_cma_object *gem;
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dma_addr_t scanout_start;
237+
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if (!plane->state->crtc || !plane->state->fb)
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return;
240+
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hdlcd = crtc_to_hdlcd_priv(plane->state->crtc);
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gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
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scanout_start = gem->paddr;
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hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
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}
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static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
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.prepare_fb = NULL,
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.cleanup_fb = NULL,
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.atomic_check = hdlcd_plane_atomic_check,
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.atomic_update = hdlcd_plane_atomic_update,
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};
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static void hdlcd_plane_destroy(struct drm_plane *plane)
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{
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drm_plane_helper_disable(plane);
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drm_plane_cleanup(plane);
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}
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static const struct drm_plane_funcs hdlcd_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.destroy = hdlcd_plane_destroy,
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.reset = drm_atomic_helper_plane_reset,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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};
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static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
270+
{
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struct hdlcd_drm_private *hdlcd = drm->dev_private;
272+
struct drm_plane *plane = NULL;
273+
u32 formats[ARRAY_SIZE(supported_formats)], i;
274+
int ret;
275+
276+
plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
277+
if (!plane)
278+
return ERR_PTR(-ENOMEM);
279+
280+
for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
281+
formats[i] = supported_formats[i].fourcc;
282+
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ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
284+
formats, ARRAY_SIZE(formats),
285+
DRM_PLANE_TYPE_PRIMARY, NULL);
286+
if (ret) {
287+
devm_kfree(drm->dev, plane);
288+
return ERR_PTR(ret);
289+
}
290+
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drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
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hdlcd->plane = plane;
293+
294+
return plane;
295+
}
296+
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void hdlcd_crtc_suspend(struct drm_crtc *crtc)
298+
{
299+
hdlcd_crtc_disable(crtc);
300+
}
301+
302+
void hdlcd_crtc_resume(struct drm_crtc *crtc)
303+
{
304+
hdlcd_crtc_enable(crtc);
305+
}
306+
307+
int hdlcd_setup_crtc(struct drm_device *drm)
308+
{
309+
struct hdlcd_drm_private *hdlcd = drm->dev_private;
310+
struct drm_plane *primary;
311+
int ret;
312+
313+
primary = hdlcd_plane_init(drm);
314+
if (IS_ERR(primary))
315+
return PTR_ERR(primary);
316+
317+
ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
318+
&hdlcd_crtc_funcs, NULL);
319+
if (ret) {
320+
hdlcd_plane_destroy(primary);
321+
devm_kfree(drm->dev, primary);
322+
return ret;
323+
}
324+
325+
drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
326+
return 0;
327+
}

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