Skip to content

Commit 8c60969

Browse files
torvaldstorvalds
committed
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Arnd Bergmann: "Most of the commits are for defconfig changes, to enable newly added drivers or features that people have started using. For the changed lines lines, we have mostly cleanups, the affected platforms are OMAP, Versatile, EP93xx, Samsung, Broadcom, i.MX, and Actions. The largest single change is the introduction of the TI "sysc" bus driver, with the intention of cleaning up more legacy code. Two new SoC platforms get added this time: - Allwinner R40 is a modernized version of the A20 chip, now with a Quad-Core ARM Cortex-A7. According to the manufacturer, it is intended for "Smart Hardware" - Broadcom Hurricane 2 (Aka Strataconnect BCM5334X) is a family of chips meant for managed gigabit ethernet switches, based around a Cortex-A9 CPU. Finally, we gain SMP support for two platforms: Renesas R-Car E2 and Amlogic Meson8/8b, which were previously added but only supported uniprocessor operation" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits) ARM: multi_v7_defconfig: Select RPMSG_VIRTIO as module ARM: multi_v7_defconfig: enable CONFIG_GPIO_UNIPHIER arm64: defconfig: enable CONFIG_GPIO_UNIPHIER ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8b ARM: meson: Add SMP bringup code for Meson8 and Meson8b ARM: smp_scu: allow the platform code to read the SCU CPU status ARM: smp_scu: add a helper for powering on a specific CPU dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation ARM: OMAP3: Delete an unnecessary variable initialisation in omap3xxx_hwmod_init() ARM: OMAP3: Use common error handling code in omap3xxx_hwmod_init() ARM: defconfig: select the right SX150X driver arm64: defconfig: Enable QCOM_IOMMU arm64: Add ThunderX drivers to defconfig arm64: defconfig: Enable Tegra PCI controller cpufreq: imx6q: Move speed grading check to cpufreq driver arm64: defconfig: re-enable Qualcomm DB410c USB ARM: configs: stm32: Add MDMA support in STM32 defconfig ARM: imx: Enable cpuidle for i.MX6DL starting at 1.1 bus: ti-sysc: Fix unbalanced pm_runtime_enable by adding remove bus: ti-sysc: mark PM functions as __maybe_unused ...
2 parents 18c83d2 + fa32475 commit 8c60969

File tree

130 files changed

+2267
-3144
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

130 files changed

+2267
-3144
lines changed

‎Documentation/arm/sunxi/README

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,11 @@ SunXi family
3333

3434
- Next Thing Co GR8 (sun5i)
3535

36+
* Single ARM Cortex-A7 based SoCs
37+
- Allwinner V3s (sun8i)
38+
+ Datasheet
39+
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
40+
3641
* Dual ARM Cortex-A7 based SoCs
3742
- Allwinner A20 (sun7i)
3843
+ User Manual
@@ -71,9 +76,11 @@ SunXi family
7176
+ Datasheet
7277
http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
7378

74-
- Allwinner V3s (sun8i)
79+
- Allwinner R40 (sun8i)
7580
+ Datasheet
76-
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
81+
https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf
82+
+ User Manual
83+
https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf
7784

7885
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
7986
- Allwinner A80

‎Documentation/devicetree/bindings/arm/amlogic/pmu.txt

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
Amlogic Meson8 and Meson8b power-management-unit:
2+
-------------------------------------------------
3+
4+
The pmu is used to turn off and on different power domains of the SoCs
5+
This includes the power to the CPU cores.
6+
7+
Required node properties:
8+
- compatible value : depending on the SoC this should be one of:
9+
"amlogic,meson8-pmu"
10+
"amlogic,meson8b-pmu"
11+
- reg : physical base address and the size of the registers window
12+
13+
Example:
14+
15+
pmu@c81000e4 {
16+
compatible = "amlogic,meson8b-pmu", "syscon";
17+
reg = <0xc81000e0 0x18>;
18+
};

‎Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
Amlogic Meson8 and Meson8b SRAM for smp bringup:
2+
------------------------------------------------
3+
4+
Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
5+
Once the core gets powered up it executes the code that is residing at a
6+
specific location.
7+
8+
Therefore a reserved section sub-node has to be added to the mmio-sram
9+
declaration.
10+
11+
Required sub-node properties:
12+
- compatible : depending on the SoC this should be one of:
13+
"amlogic,meson8-smp-sram"
14+
"amlogic,meson8b-smp-sram"
15+
16+
The rest of the properties should follow the generic mmio-sram discription
17+
found in ../../misc/sram.txt
18+
19+
Example:
20+
21+
sram: sram@d9000000 {
22+
compatible = "mmio-sram";
23+
reg = <0xd9000000 0x20000>;
24+
#address-cells = <1>;
25+
#size-cells = <1>;
26+
ranges = <0 0xd9000000 0x20000>;
27+
28+
smp-sram@1ff80 {
29+
compatible = "amlogic,meson8b-smp-sram";
30+
reg = <0x1ff80 0x8>;
31+
};
32+
};

‎Documentation/devicetree/bindings/arm/cpus.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,8 @@ described below.
197197
"actions,s500-smp"
198198
"allwinner,sun6i-a31"
199199
"allwinner,sun8i-a23"
200+
"amlogic,meson8-smp"
201+
"amlogic,meson8b-smp"
200202
"arm,realview-smp"
201203
"brcm,bcm11351-cpu-method"
202204
"brcm,bcm23550"

‎Documentation/devicetree/bindings/arm/omap/ctrl.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,8 @@ Required properties:
2121
"ti,omap3-scm"
2222
"ti,omap4-scm-core"
2323
"ti,omap4-scm-padconf-core"
24+
"ti,omap4-scm-wkup"
25+
"ti,omap4-scm-padconf-wkup"
2426
"ti,omap5-scm-core"
2527
"ti,omap5-scm-padconf-core"
2628
"ti,dra7-scm-core"

‎Documentation/devicetree/bindings/arm/sunxi.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,8 @@ using one of the following compatible strings:
1414
allwinner,sun8i-a83t
1515
allwinner,sun8i-h2-plus
1616
allwinner,sun8i-h3
17+
allwinner-sun8i-r40
18+
allwinner,sun8i-v3s
1719
allwinner,sun9i-a80
1820
allwinner,sun50i-a64
1921
nextthing,gr8

‎Documentation/devicetree/bindings/bus/ti-sysc.txt

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
1+
Texas Instruments sysc interconnect target module wrapper binding
2+
3+
Texas Instruments SoCs can have a generic interconnect target module
4+
hardware for devices connected to various interconnects such as L3
5+
interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
6+
is mostly used for interaction between module and PRCM. It participates
7+
in the OCP Disconnect Protocol but other than that is mostly independent
8+
of the interconnect.
9+
10+
Each interconnect target module can have one or more devices connected to
11+
it. There is a set of control registers for managing interconnect target
12+
module clocks, idle modes and interconnect level resets for the module.
13+
14+
These control registers are sprinkled into the unused register address
15+
space of the first child device IP block managed by the interconnect
16+
target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.
17+
18+
Required standard properties:
19+
20+
- compatible shall be one of the following generic types:
21+
22+
"ti,sysc-omap2"
23+
"ti,sysc-omap4"
24+
"ti,sysc-omap4-simple"
25+
26+
or one of the following derivative types for hardware
27+
needing special workarounds:
28+
29+
"ti,sysc-omap3430-sr"
30+
"ti,sysc-omap3630-sr"
31+
"ti,sysc-omap4-sr"
32+
"ti,sysc-omap3-sham"
33+
"ti,sysc-omap-aes"
34+
"ti,sysc-mcasp"
35+
"ti,sysc-usb-host-fs"
36+
37+
- reg shall have register areas implemented for the interconnect
38+
target module in question such as revision, sysc and syss
39+
40+
- reg-names shall contain the register names implemented for the
41+
interconnect target module in question such as
42+
"rev, "sysc", and "syss"
43+
44+
- ranges shall contain the interconnect target module IO range
45+
available for one or more child device IP blocks managed
46+
by the interconnect target module, the ranges may include
47+
multiple ranges such as device L4 range for control and
48+
parent L3 range for DMA access
49+
50+
Optional properties:
51+
52+
- clocks clock specifier for each name in the clock-names as
53+
specified in the binding documentation for ti-clkctrl,
54+
typically available for all interconnect targets on TI SoCs
55+
based on omap4 except if it's read-only register in hwauto
56+
mode as for example omap4 L4_CFG_CLKCTRL
57+
58+
- clock-names should contain at least "fck", and optionally also "ick"
59+
depending on the SoC and the interconnect target module
60+
61+
- ti,hwmods optional TI interconnect module name to use legacy
62+
hwmod platform data
63+
64+
65+
Example: Single instance of MUSB controller on omap4 using interconnect ranges
66+
using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
67+
68+
target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
69+
compatible = "ti,sysc-omap2";
70+
ti,hwmods = "usb_otg_hs";
71+
reg = <0x2b400 0x4>,
72+
<0x2b404 0x4>,
73+
<0x2b408 0x4>;
74+
reg-names = "rev", "sysc", "syss";
75+
clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
76+
clock-names = "fck";
77+
#address-cells = <1>;
78+
#size-cells = <1>;
79+
ranges = <0 0x2b000 0x1000>;
80+
81+
usb_otg_hs: otg@0 {
82+
compatible = "ti,omap4-musb";
83+
reg = <0x0 0x7ff>;
84+
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
85+
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
86+
usb-phy = <&usb2_phy>;
87+
...
88+
};
89+
};
90+
91+
Note that other SoCs, such as am335x can have multipe child devices. On am335x
92+
there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
93+
instance as children of a single interconnet target module.

‎Documentation/devicetree/bindings/memory-controllers/ti/emif.txt

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it.
77

88
Required properties:
99
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
10-
is the IP revision of the specific EMIF instance.
11-
For am437x should be ti,emif-am4372.
10+
is the IP revision of the specific EMIF instance. For newer controllers,
11+
compatible should be one of the following:
12+
"ti,emif-am3352"
13+
"ti,emif-am4372"
1214

1315
- phy-type : <u32> indicating the DDR phy type. Following are the
1416
allowed values

‎Documentation/devicetree/bindings/power/ti-smartreflex.txt

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
Texas Instruments SmartReflex binding
2+
3+
SmartReflex is used to set and adjust the SoC operating points.
4+
5+
6+
Required properties:
7+
8+
compatible: Shall be one of the following:
9+
"ti,omap3-smartreflex-core"
10+
"ti,omap3-smartreflex-iva"
11+
"ti,omap4-smartreflex-core"
12+
"ti,omap4-smartreflex-mpu"
13+
"ti,omap4-smartreflex-iva"
14+
15+
reg: Shall contain the device instance IO range
16+
17+
interrupts: Shall contain the device instance interrupt
18+
19+
20+
Optional properties:
21+
22+
ti,hwmods: Shall contain the TI interconnect module name if needed
23+
by the SoC
24+
25+
26+
Example:
27+
28+
smartreflex_iva: smartreflex@4a0db000 {
29+
compatible = "ti,omap4-smartreflex-iva";
30+
reg = <0x4a0db000 0x80>;
31+
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
32+
ti,hwmods = "smartreflex_iva";
33+
};
34+
35+
smartreflex_core: smartreflex@4a0dd000 {
36+
compatible = "ti,omap4-smartreflex-core";
37+
reg = <0x4a0dd000 0x80>;
38+
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
39+
ti,hwmods = "smartreflex_core";
40+
};
41+
42+
smartreflex_mpu: smartreflex@4a0d9000 {
43+
compatible = "ti,omap4-smartreflex-mpu";
44+
reg = <0x4a0d9000 0x80>;
45+
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
46+
ti,hwmods = "smartreflex_mpu";
47+
};

‎MAINTAINERS

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2162,7 +2162,6 @@ F: sound/soc/zte/
21622162

21632163
ARM/ZYNQ ARCHITECTURE
21642164
M: Michal Simek <michal.simek@xilinx.com>
2165-
R: Sören Brinkmann <soren.brinkmann@xilinx.com>
21662165
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
21672166
W: http://wiki.xilinx.com
21682167
T: git https://github.com/Xilinx/linux-xlnx.git
@@ -2937,6 +2936,7 @@ N: bcm583*
29372936
N: bcm585*
29382937
N: bcm586*
29392938
N: bcm88312
2939+
N: hr2
29402940
F: arch/arm64/boot/dts/broadcom/ns2*
29412941
F: drivers/clk/bcm/clk-ns*
29422942
F: drivers/pinctrl/bcm/pinctrl-ns*

‎arch/arm/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -371,7 +371,7 @@ config ARCH_EBSA110
371371

372372
config ARCH_EP93XX
373373
bool "EP93xx-based"
374-
select ARCH_HAS_HOLES_MEMORYMODEL
374+
select ARCH_SPARSEMEM_ENABLE
375375
select ARM_AMBA
376376
imply ARM_PATCH_PHYS_VIRT
377377
select ARM_VIC

‎arch/arm/Kconfig.debug

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -170,6 +170,11 @@ choice
170170
depends on ARCH_BCM_5301X || ARCH_BCM_NSP
171171
select DEBUG_UART_8250
172172

173+
config DEBUG_BCM_HR2
174+
bool "Kernel low-level debugging on Hurricane 2 UART2"
175+
depends on ARCH_BCM_HR2
176+
select DEBUG_UART_8250
177+
173178
config DEBUG_BCM_KONA_UART
174179
bool "Kernel low-level debugging messages via BCM KONA UART"
175180
depends on ARCH_BCM_MOBILE
@@ -912,6 +917,13 @@ choice
912917
Say Y here if you want kernel low-level debugging support
913918
via SCIF2 on Renesas R-Car E2 (R8A7794).
914919

920+
config DEBUG_RCAR_GEN2_SCIF4
921+
bool "Kernel low-level debugging messages via SCIF4 on R8A7745"
922+
depends on ARCH_R8A7745
923+
help
924+
Say Y here if you want kernel low-level debugging support
925+
via SCIF4 on Renesas RZ/G1E (R8A7745).
926+
915927
config DEBUG_RMOBILE_SCIFA0
916928
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
917929
depends on ARCH_R8A73A4
@@ -1452,6 +1464,7 @@ config DEBUG_LL_INCLUDE
14521464
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
14531465
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
14541466
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
1467+
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
14551468
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
14561469
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
14571470
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
@@ -1509,6 +1522,7 @@ config DEBUG_UART_PHYS
15091522
default 0x11009000 if DEBUG_MT8135_UART3
15101523
default 0x16000000 if DEBUG_INTEGRATOR
15111524
default 0x18000300 if DEBUG_BCM_5301X
1525+
default 0x18000400 if DEBUG_BCM_HR2
15121526
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
15131527
default 0x18020000 if DEBUG_SIRFATLAS7_UART1
15141528
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
@@ -1571,6 +1585,7 @@ config DEBUG_UART_PHYS
15711585
default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
15721586
default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
15731587
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
1588+
default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
15741589
default 0xe8008000 if DEBUG_R7S72100_SCIF2
15751590
default 0xf0000be0 if ARCH_EBSA110
15761591
default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
@@ -1605,6 +1620,7 @@ config DEBUG_UART_PHYS
16051620
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
16061621
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
16071622
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
1623+
DEBUG_RCAR_GEN2_SCIF4 || \
16081624
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
16091625
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
16101626
DEBUG_S3C64XX_UART || \
@@ -1624,6 +1640,7 @@ config DEBUG_UART_VIRT
16241640
default 0xf01fb000 if DEBUG_NOMADIK_UART
16251641
default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836
16261642
default 0xf1000300 if DEBUG_BCM_5301X
1643+
default 0xf1000400 if DEBUG_BCM_HR2
16271644
default 0xf1002000 if DEBUG_MT8127_UART0
16281645
default 0xf1006000 if DEBUG_MT6589_UART0
16291646
default 0xf1009000 if DEBUG_MT8135_UART3
@@ -1729,7 +1746,8 @@ config DEBUG_UART_8250_SHIFT
17291746
int "Register offset shift for the 8250 debug UART"
17301747
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
17311748
default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \
1732-
DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || DEBUG_OMAP7XXUART3
1749+
DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \
1750+
DEBUG_OMAP7XXUART3
17331751
default 2
17341752

17351753
config DEBUG_UART_8250_WORD

‎arch/arm/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
149149
endif
150150
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
151151
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
152+
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
152153
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
153154

154155
# Machine directory name. This list is sorted alphanumerically

‎arch/arm/boot/dts/am33xx.dtsi

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -130,9 +130,11 @@
130130
};
131131
};
132132

133-
pmu {
133+
pmu@4b000000 {
134134
compatible = "arm,cortex-a8-pmu";
135135
interrupts = <3>;
136+
reg = <0x4b000000 0x1000000>;
137+
ti,hwmods = "debugss";
136138
};
137139

138140
/*
@@ -929,6 +931,12 @@
929931
};
930932
};
931933

934+
emif: emif@4c000000 {
935+
compatible = "ti,emif-am3352";
936+
reg = <0x4c000000 0x1000000>;
937+
ti,hwmods = "emif";
938+
};
939+
932940
gpmc: gpmc@50000000 {
933941
compatible = "ti,am3352-gpmc";
934942
ti,hwmods = "gpmc";

0 commit comments

Comments
 (0)