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582 | 582 | status = "disabled";
|
583 | 583 | };
|
584 | 584 |
|
| 585 | + crypto0: crypto@ff8b0000 { |
| 586 | + compatible = "rockchip,rk3399-crypto"; |
| 587 | + reg = <0x0 0xff8b0000 0x0 0x4000>; |
| 588 | + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; |
| 589 | + clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>; |
| 590 | + clock-names = "hclk_master", "hclk_slave", "sclk"; |
| 591 | + resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>; |
| 592 | + reset-names = "master", "lave", "crypto"; |
| 593 | + }; |
| 594 | + |
| 595 | + crypto1: crypto@ff8b8000 { |
| 596 | + compatible = "rockchip,rk3399-crypto"; |
| 597 | + reg = <0x0 0xff8b8000 0x0 0x4000>; |
| 598 | + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; |
| 599 | + clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>; |
| 600 | + clock-names = "hclk_master", "hclk_slave", "sclk"; |
| 601 | + resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>; |
| 602 | + reset-names = "master", "slave", "crypto"; |
| 603 | + }; |
| 604 | + |
585 | 605 | i2c1: i2c@ff110000 {
|
586 | 606 | compatible = "rockchip,rk3399-i2c";
|
587 | 607 | reg = <0x0 0xff110000 0x0 0x1000>;
|
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