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pinctrl: aspeed-g5: Fix pin association of SPI1 function
The SPI1 function was associated with the wrong pins: The functions that those pins provide is either an SPI debug or passthrough function coupled to SPI1. Make the SPI1 mux function configure the relevant pins and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins that were already defined. The notation used in the datasheet's multi-function pin table for the SoC is often creative: in this case the SYS* signals are enabled by a single bit, which is nothing unusual on its own, but in this case the bit was also participating in a multi-bit bitfield and therefore represented multiple functions. This fact was overlooked in the original patch. Fixes: 56e57cb (pinctrl: Add pinctrl-aspeed-g5 driver) Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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‎Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,9 @@ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
4343

4444
GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
4545
I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
46-
RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8
46+
RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
47+
TIMER7 TIMER8 VGABIOSROM
48+
4749

4850
Examples:
4951

‎drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

Lines changed: 78 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -186,24 +186,84 @@ MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
186186

187187
FUNC_GROUP_DECL(GPIE0, B20, C20);
188188

189-
#define SPI1_DESC SIG_DESC_SET(HW_STRAP1, 13)
189+
#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
190+
#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
191+
#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
192+
190193
#define C18 64
191-
SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SPI1, COND1, SPI1_DESC);
194+
SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
195+
SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
196+
SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
192197
SS_PIN_DECL(C18, GPIOI0, SYSCS);
193198

194199
#define E15 65
195-
SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SPI1, COND1, SPI1_DESC);
200+
SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
201+
SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
202+
SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
196203
SS_PIN_DECL(E15, GPIOI1, SYSCK);
197204

198-
#define A14 66
199-
SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SPI1, COND1, SPI1_DESC);
200-
SS_PIN_DECL(A14, GPIOI2, SYSMOSI);
205+
#define B16 66
206+
SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
207+
SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
208+
SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
209+
SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
201210

202211
#define C16 67
203-
SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SPI1, COND1, SPI1_DESC);
212+
SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
213+
SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
214+
SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
204215
SS_PIN_DECL(C16, GPIOI3, SYSMISO);
205216

206-
FUNC_GROUP_DECL(SPI1, C18, E15, A14, C16);
217+
#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
218+
219+
#define B15 68
220+
SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC);
221+
SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
222+
SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
223+
SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
224+
SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
225+
SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
226+
SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC);
227+
MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
228+
229+
#define C15 69
230+
SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC);
231+
SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
232+
SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
233+
SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
234+
SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
235+
SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
236+
SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC);
237+
MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
238+
239+
#define A14 70
240+
SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC);
241+
SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
242+
SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
243+
SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1),
244+
SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
245+
SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
246+
SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC);
247+
MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
248+
249+
#define A15 71
250+
SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC);
251+
SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
252+
SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
253+
SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1),
254+
SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
255+
SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
256+
SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC);
257+
MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
258+
259+
FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
260+
FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
261+
FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
262+
FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
263+
264+
#define R2 72
265+
SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
266+
SS_PIN_DECL(R2, GPIOJ0, SGPMCK);
207267

208268
#define L2 73
209269
SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
@@ -580,6 +640,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
580640
ASPEED_PINCTRL_PIN(A12),
581641
ASPEED_PINCTRL_PIN(A13),
582642
ASPEED_PINCTRL_PIN(A14),
643+
ASPEED_PINCTRL_PIN(A15),
583644
ASPEED_PINCTRL_PIN(A2),
584645
ASPEED_PINCTRL_PIN(A3),
585646
ASPEED_PINCTRL_PIN(A4),
@@ -592,6 +653,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
592653
ASPEED_PINCTRL_PIN(B12),
593654
ASPEED_PINCTRL_PIN(B13),
594655
ASPEED_PINCTRL_PIN(B14),
656+
ASPEED_PINCTRL_PIN(B15),
657+
ASPEED_PINCTRL_PIN(B16),
595658
ASPEED_PINCTRL_PIN(B2),
596659
ASPEED_PINCTRL_PIN(B20),
597660
ASPEED_PINCTRL_PIN(B3),
@@ -603,6 +666,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
603666
ASPEED_PINCTRL_PIN(C12),
604667
ASPEED_PINCTRL_PIN(C13),
605668
ASPEED_PINCTRL_PIN(C14),
669+
ASPEED_PINCTRL_PIN(C15),
606670
ASPEED_PINCTRL_PIN(C16),
607671
ASPEED_PINCTRL_PIN(C18),
608672
ASPEED_PINCTRL_PIN(C2),
@@ -691,11 +755,14 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
691755
ASPEED_PINCTRL_GROUP(RMII2),
692756
ASPEED_PINCTRL_GROUP(SD1),
693757
ASPEED_PINCTRL_GROUP(SPI1),
758+
ASPEED_PINCTRL_GROUP(SPI1DEBUG),
759+
ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
694760
ASPEED_PINCTRL_GROUP(TIMER4),
695761
ASPEED_PINCTRL_GROUP(TIMER5),
696762
ASPEED_PINCTRL_GROUP(TIMER6),
697763
ASPEED_PINCTRL_GROUP(TIMER7),
698764
ASPEED_PINCTRL_GROUP(TIMER8),
765+
ASPEED_PINCTRL_GROUP(VGABIOSROM),
699766
};
700767

701768
static const struct aspeed_pin_function aspeed_g5_functions[] = {
@@ -733,11 +800,14 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
733800
ASPEED_PINCTRL_FUNC(RMII2),
734801
ASPEED_PINCTRL_FUNC(SD1),
735802
ASPEED_PINCTRL_FUNC(SPI1),
803+
ASPEED_PINCTRL_FUNC(SPI1DEBUG),
804+
ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
736805
ASPEED_PINCTRL_FUNC(TIMER4),
737806
ASPEED_PINCTRL_FUNC(TIMER5),
738807
ASPEED_PINCTRL_FUNC(TIMER6),
739808
ASPEED_PINCTRL_FUNC(TIMER7),
740809
ASPEED_PINCTRL_FUNC(TIMER8),
810+
ASPEED_PINCTRL_FUNC(VGABIOSROM),
741811
};
742812

743813
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {

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