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arm64: dts: renesas: Initial r8a774a1 SoC device tree
Basic support for the RZ/G2M SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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‎arch/arm64/boot/dts/renesas/r8a774a1.dtsi

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a774a1 SoC
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/ {
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compatible = "renesas,r8a774a1";
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#address-cells = <2>;
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#size-cells = <2>;
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency
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* clocks by default.
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* Boards that provide audio clocks should override them.
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*/
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a57_0: cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc 0>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE 0>;
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};
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a57_1: cpu@1 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x1>;
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device_type = "cpu";
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power-domains = <&sysc 1>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE 0>;
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};
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L2_CA57: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc 12>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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/* External PCIe clock - can be overridden by the board */
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pcie_bus_clk: pcie_bus {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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pmu_a57 {
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compatible = "arm,cortex-a57-pmu";
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interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a57_0>, <&a57_1>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a774a1-cpg-mssr";
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reg = <0 0xe6150000 0 0x0bb0>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a774a1-rst";
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reg = <0 0xe6160000 0 0x018c>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a774a1-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x20000>,
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc 32>;
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resets = <&cpg 408>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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/* External USB clocks - can be overridden by the board */
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usb3s0_clk: usb3s0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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usb_extal_clk: usb_extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};

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