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lynxeye-devShawn Guo
lynxeye-dev
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Shawn Guo
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arm64: add support for i.MX8M EVK board
This is the evaluation kit board for the i.MX8M. The current level of support yields a working console and is able to boot userspace from SD card or Network. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> (v1) Reviewed-by: Rob Herring <robh@kernel.org> (v3) Tested-by: Tested-by: Baruch Siach <baruch@tkos.co.il> (v1) Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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‎arch/arm64/boot/dts/freescale/Makefile

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@@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb

‎arch/arm64/boot/dts/freescale/imx8mq-evk.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2017 NXP
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* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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/dts-v1/;
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#include "imx8mq.dtsi"
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/ {
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model = "NXP i.MX8MQ EVK";
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compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
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chosen {
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stdout-path = &uart1;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x00000000 0x40000000 0 0xc0000000>;
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};
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reg_usdhc2_vmmc: regulator-vsd-3v3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2>;
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@8 {
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compatible = "fsl,pfuze100";
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reg = <0x8>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <975000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1675000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1625000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <3075000>;
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regulator-max-microvolt = <3625000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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vqmmc-supply = <&sw4_reg>;
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bus-width = <8>;
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non-removable;
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no-sd;
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no-sdio;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <&reg_usdhc2_vmmc>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_reg_usdhc2: regusdhc2grpgpio {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
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MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1-200grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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};

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