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Merge branch 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
radeon and amdgpu fixes for 4.5. Three regression fixes and some fixups for the error handling in the vblank regression fixes from earlier. * 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux: Revert "drm/radeon/pm: adjust display configuration after powerstate" drm/amdgpu/dp: add back special handling for NUTMEG drm/radeon/dp: add back special handling for NUTMEG drm/radeon: Fix error handling in radeon_flip_work_func. drm/amdgpu: Fix error handling in amdgpu_flip_work_func.
2 parents dad82ea + d74e766 commit 9138301

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5 files changed

+38
-15
lines changed

5 files changed

+38
-15
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
9696
* In practice this won't execute very often unless on very fast
9797
* machines because the time window for this to happen is very small.
9898
*/
99-
while (amdgpuCrtc->enabled && repcnt--) {
99+
while (amdgpuCrtc->enabled && --repcnt) {
100100
/* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
101101
* start in hpos, and to the "fudged earlier" vblank start in
102102
* vpos.
@@ -112,13 +112,13 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
112112
break;
113113

114114
/* Sleep at least until estimated real start of hw vblank */
115-
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
116115
min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
117116
if (min_udelay > vblank->framedur_ns / 2000) {
118117
/* Don't wait ridiculously long - something is wrong */
119118
repcnt = 0;
120119
break;
121120
}
121+
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
122122
usleep_range(min_udelay, 2 * min_udelay);
123123
spin_lock_irqsave(&crtc->dev->event_lock, flags);
124124
};

‎drivers/gpu/drm/amd/amdgpu/atombios_dp.c

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -265,15 +265,27 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
265265
unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
266266
unsigned lane_num, i, max_pix_clock;
267267

268-
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
269-
for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
270-
max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
268+
if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
269+
ENCODER_OBJECT_ID_NUTMEG) {
270+
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
271+
max_pix_clock = (lane_num * 270000 * 8) / bpp;
271272
if (max_pix_clock >= pix_clock) {
272273
*dp_lanes = lane_num;
273-
*dp_rate = link_rates[i];
274+
*dp_rate = 270000;
274275
return 0;
275276
}
276277
}
278+
} else {
279+
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
280+
for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
281+
max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
282+
if (max_pix_clock >= pix_clock) {
283+
*dp_lanes = lane_num;
284+
*dp_rate = link_rates[i];
285+
return 0;
286+
}
287+
}
288+
}
277289
}
278290

279291
return -EINVAL;

‎drivers/gpu/drm/radeon/atombios_dp.c

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -315,15 +315,27 @@ int radeon_dp_get_dp_link_config(struct drm_connector *connector,
315315
unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
316316
unsigned lane_num, i, max_pix_clock;
317317

318-
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
319-
for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
320-
max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
318+
if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
319+
ENCODER_OBJECT_ID_NUTMEG) {
320+
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
321+
max_pix_clock = (lane_num * 270000 * 8) / bpp;
321322
if (max_pix_clock >= pix_clock) {
322323
*dp_lanes = lane_num;
323-
*dp_rate = link_rates[i];
324+
*dp_rate = 270000;
324325
return 0;
325326
}
326327
}
328+
} else {
329+
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
330+
for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
331+
max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
332+
if (max_pix_clock >= pix_clock) {
333+
*dp_lanes = lane_num;
334+
*dp_rate = link_rates[i];
335+
return 0;
336+
}
337+
}
338+
}
327339
}
328340

329341
return -EINVAL;

‎drivers/gpu/drm/radeon/radeon_display.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -455,7 +455,7 @@ static void radeon_flip_work_func(struct work_struct *__work)
455455
* In practice this won't execute very often unless on very fast
456456
* machines because the time window for this to happen is very small.
457457
*/
458-
while (radeon_crtc->enabled && repcnt--) {
458+
while (radeon_crtc->enabled && --repcnt) {
459459
/* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
460460
* start in hpos, and to the "fudged earlier" vblank start in
461461
* vpos.
@@ -471,13 +471,13 @@ static void radeon_flip_work_func(struct work_struct *__work)
471471
break;
472472

473473
/* Sleep at least until estimated real start of hw vblank */
474-
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
475474
min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
476475
if (min_udelay > vblank->framedur_ns / 2000) {
477476
/* Don't wait ridiculously long - something is wrong */
478477
repcnt = 0;
479478
break;
480479
}
480+
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
481481
usleep_range(min_udelay, 2 * min_udelay);
482482
spin_lock_irqsave(&crtc->dev->event_lock, flags);
483483
};

‎drivers/gpu/drm/radeon/radeon_pm.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1079,6 +1079,8 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
10791079

10801080
/* update display watermarks based on new power state */
10811081
radeon_bandwidth_update(rdev);
1082+
/* update displays */
1083+
radeon_dpm_display_configuration_changed(rdev);
10821084

10831085
/* wait for the rings to drain */
10841086
for (i = 0; i < RADEON_NUM_RINGS; i++) {
@@ -1095,9 +1097,6 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
10951097

10961098
radeon_dpm_post_set_power_state(rdev);
10971099

1098-
/* update displays */
1099-
radeon_dpm_display_configuration_changed(rdev);
1100-
11011100
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
11021101
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
11031102
rdev->pm.dpm.single_display = single_display;

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