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Suzuki K Poulosewildea01
Suzuki K Poulose
authored and
wildea01
committed
arm64: cpufeature: Add scope for capability check
Add scope parameter to the arm64_cpu_capabilities::matches(), so that this can be reused for checking the capability on a given CPU vs the system wide. The system uses the default scope associated with the capability for initialising the CPU_HWCAPs and ELF_HWCAPs. Cc: James Morse <james.morse@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Will Deacon <will.deacon@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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-61
lines changed

3 files changed

+83
-61
lines changed

‎arch/arm64/include/asm/cpufeature.h

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,10 +78,17 @@ struct arm64_ftr_reg {
7878
struct arm64_ftr_bits *ftr_bits;
7979
};
8080

81+
/* scope of capability check */
82+
enum {
83+
SCOPE_SYSTEM,
84+
SCOPE_LOCAL_CPU,
85+
};
86+
8187
struct arm64_cpu_capabilities {
8288
const char *desc;
8389
u16 capability;
84-
bool (*matches)(const struct arm64_cpu_capabilities *);
90+
int def_scope; /* default scope */
91+
bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
8592
void (*enable)(void *); /* Called on all active CPUs */
8693
union {
8794
struct { /* To be used for erratum handling only */

‎arch/arm64/kernel/cpu_errata.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,14 +22,16 @@
2222
#include <asm/cpufeature.h>
2323

2424
static bool __maybe_unused
25-
is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
25+
is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
2626
{
27+
WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
2728
return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model,
2829
entry->midr_range_min,
2930
entry->midr_range_max);
3031
}
3132

3233
#define MIDR_RANGE(model, min, max) \
34+
.def_scope = SCOPE_LOCAL_CPU, \
3335
.matches = is_affected_midr_range, \
3436
.midr_model = model, \
3537
.midr_range_min = min, \

‎arch/arm64/kernel/cpufeature.c

Lines changed: 72 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,8 @@ DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
7171

7272
/* meta feature for alternatives */
7373
static bool __maybe_unused
74-
cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
74+
cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
75+
7576

7677
static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
7778
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
@@ -626,6 +627,49 @@ u64 read_system_reg(u32 id)
626627
return regp->sys_val;
627628
}
628629

630+
/*
631+
* __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
632+
* Read the system register on the current CPU
633+
*/
634+
static u64 __raw_read_system_reg(u32 sys_id)
635+
{
636+
switch (sys_id) {
637+
case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
638+
case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
639+
case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
640+
case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
641+
case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
642+
case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
643+
case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
644+
case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
645+
case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
646+
case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
647+
case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
648+
case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
649+
case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
650+
case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
651+
case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
652+
case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
653+
654+
case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
655+
case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
656+
case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
657+
case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
658+
case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
659+
case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
660+
case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
661+
case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
662+
case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
663+
664+
case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
665+
case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
666+
case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
667+
default:
668+
BUG();
669+
return 0;
670+
}
671+
}
672+
629673
#include <linux/irqchip/arm-gic-v3.h>
630674

631675
static bool
@@ -637,19 +681,24 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
637681
}
638682

639683
static bool
640-
has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
684+
has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
641685
{
642686
u64 val;
643687

644-
val = read_system_reg(entry->sys_reg);
688+
WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
689+
if (scope == SCOPE_SYSTEM)
690+
val = read_system_reg(entry->sys_reg);
691+
else
692+
val = __raw_read_system_reg(entry->sys_reg);
693+
645694
return feature_matches(val, entry);
646695
}
647696

648-
static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
697+
static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
649698
{
650699
bool has_sre;
651700

652-
if (!has_cpuid_feature(entry))
701+
if (!has_cpuid_feature(entry, scope))
653702
return false;
654703

655704
has_sre = gic_enable_sre();
@@ -660,7 +709,7 @@ static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
660709
return has_sre;
661710
}
662711

663-
static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
712+
static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
664713
{
665714
u32 midr = read_cpuid_id();
666715
u32 rv_min, rv_max;
@@ -672,7 +721,7 @@ static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
672721
return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
673722
}
674723

675-
static bool runs_at_el2(const struct arm64_cpu_capabilities *entry)
724+
static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
676725
{
677726
return is_kernel_in_hyp_mode();
678727
}
@@ -681,6 +730,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
681730
{
682731
.desc = "GIC system register CPU interface",
683732
.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
733+
.def_scope = SCOPE_SYSTEM,
684734
.matches = has_useable_gicv3_cpuif,
685735
.sys_reg = SYS_ID_AA64PFR0_EL1,
686736
.field_pos = ID_AA64PFR0_GIC_SHIFT,
@@ -691,6 +741,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
691741
{
692742
.desc = "Privileged Access Never",
693743
.capability = ARM64_HAS_PAN,
744+
.def_scope = SCOPE_SYSTEM,
694745
.matches = has_cpuid_feature,
695746
.sys_reg = SYS_ID_AA64MMFR1_EL1,
696747
.field_pos = ID_AA64MMFR1_PAN_SHIFT,
@@ -703,6 +754,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
703754
{
704755
.desc = "LSE atomic instructions",
705756
.capability = ARM64_HAS_LSE_ATOMICS,
757+
.def_scope = SCOPE_SYSTEM,
706758
.matches = has_cpuid_feature,
707759
.sys_reg = SYS_ID_AA64ISAR0_EL1,
708760
.field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
@@ -713,12 +765,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
713765
{
714766
.desc = "Software prefetching using PRFM",
715767
.capability = ARM64_HAS_NO_HW_PREFETCH,
768+
.def_scope = SCOPE_SYSTEM,
716769
.matches = has_no_hw_prefetch,
717770
},
718771
#ifdef CONFIG_ARM64_UAO
719772
{
720773
.desc = "User Access Override",
721774
.capability = ARM64_HAS_UAO,
775+
.def_scope = SCOPE_SYSTEM,
722776
.matches = has_cpuid_feature,
723777
.sys_reg = SYS_ID_AA64MMFR2_EL1,
724778
.field_pos = ID_AA64MMFR2_UAO_SHIFT,
@@ -729,17 +783,20 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
729783
#ifdef CONFIG_ARM64_PAN
730784
{
731785
.capability = ARM64_ALT_PAN_NOT_UAO,
786+
.def_scope = SCOPE_SYSTEM,
732787
.matches = cpufeature_pan_not_uao,
733788
},
734789
#endif /* CONFIG_ARM64_PAN */
735790
{
736791
.desc = "Virtualization Host Extensions",
737792
.capability = ARM64_HAS_VIRT_HOST_EXTN,
793+
.def_scope = SCOPE_SYSTEM,
738794
.matches = runs_at_el2,
739795
},
740796
{
741797
.desc = "32-bit EL0 Support",
742798
.capability = ARM64_HAS_32BIT_EL0,
799+
.def_scope = SCOPE_SYSTEM,
743800
.matches = has_cpuid_feature,
744801
.sys_reg = SYS_ID_AA64PFR0_EL1,
745802
.sign = FTR_UNSIGNED,
@@ -752,6 +809,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
752809
#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
753810
{ \
754811
.desc = #cap, \
812+
.def_scope = SCOPE_SYSTEM, \
755813
.matches = has_cpuid_feature, \
756814
.sys_reg = reg, \
757815
.field_pos = field, \
@@ -834,15 +892,15 @@ static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
834892
static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
835893
{
836894
for (; hwcaps->matches; hwcaps++)
837-
if (hwcaps->matches(hwcaps))
895+
if (hwcaps->matches(hwcaps, hwcaps->def_scope))
838896
cap_set_elf_hwcap(hwcaps);
839897
}
840898

841899
void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
842900
const char *info)
843901
{
844902
for (; caps->matches; caps++) {
845-
if (!caps->matches(caps))
903+
if (!caps->matches(caps, caps->def_scope))
846904
continue;
847905

848906
if (!cpus_have_cap(caps->capability) && caps->desc)
@@ -878,48 +936,6 @@ static inline void set_sys_caps_initialised(void)
878936
sys_caps_initialised = true;
879937
}
880938

881-
/*
882-
* __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
883-
*/
884-
static u64 __raw_read_system_reg(u32 sys_id)
885-
{
886-
switch (sys_id) {
887-
case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
888-
case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
889-
case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
890-
case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
891-
case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
892-
case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
893-
case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
894-
case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
895-
case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
896-
case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
897-
case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
898-
case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
899-
case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
900-
case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
901-
case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
902-
case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
903-
904-
case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
905-
case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
906-
case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
907-
case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
908-
case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
909-
case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
910-
case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
911-
case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
912-
case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
913-
914-
case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
915-
case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
916-
case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
917-
default:
918-
BUG();
919-
return 0;
920-
}
921-
}
922-
923939
/*
924940
* Check for CPU features that are used in early boot
925941
* based on the Boot CPU value.
@@ -934,28 +950,25 @@ static void
934950
verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
935951
{
936952

937-
for (; caps->matches; caps++) {
938-
if (!cpus_have_elf_hwcap(caps))
939-
continue;
940-
if (!feature_matches(__raw_read_system_reg(caps->sys_reg), caps)) {
953+
for (; caps->matches; caps++)
954+
if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
941955
pr_crit("CPU%d: missing HWCAP: %s\n",
942956
smp_processor_id(), caps->desc);
943957
cpu_die_early();
944958
}
945-
}
946959
}
947960

948961
static void
949962
verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
950963
{
951964
for (; caps->matches; caps++) {
952-
if (!cpus_have_cap(caps->capability) || !caps->sys_reg)
965+
if (!cpus_have_cap(caps->capability))
953966
continue;
954967
/*
955968
* If the new CPU misses an advertised feature, we cannot proceed
956969
* further, park the cpu.
957970
*/
958-
if (!feature_matches(__raw_read_system_reg(caps->sys_reg), caps)) {
971+
if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
959972
pr_crit("CPU%d: missing feature: %s\n",
960973
smp_processor_id(), caps->desc);
961974
cpu_die_early();
@@ -1026,7 +1039,7 @@ void __init setup_cpu_features(void)
10261039
}
10271040

10281041
static bool __maybe_unused
1029-
cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
1042+
cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
10301043
{
10311044
return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
10321045
}

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