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| 1 | +* Mobiveil AXI PCIe Root Port Bridge DT description |
| 2 | + |
| 3 | +Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP |
| 4 | +has up to 8 outbound and inbound windows for the address translation. |
| 5 | + |
| 6 | +Required properties: |
| 7 | +- #address-cells: Address representation for root ports, set to <3> |
| 8 | +- #size-cells: Size representation for root ports, set to <2> |
| 9 | +- #interrupt-cells: specifies the number of cells needed to encode an |
| 10 | + interrupt source. The value must be 1. |
| 11 | +- compatible: Should contain "mbvl,gpex40-pcie" |
| 12 | +- reg: Should contain PCIe registers location and length |
| 13 | + "config_axi_slave": PCIe controller registers |
| 14 | + "csr_axi_slave" : Bridge config registers |
| 15 | + "gpio_slave" : GPIO registers to control slot power |
| 16 | + "apb_csr" : MSI registers |
| 17 | + |
| 18 | +- device_type: must be "pci" |
| 19 | +- apio-wins : number of requested apio outbound windows |
| 20 | + default 2 outbound windows are configured - |
| 21 | + 1. Config window |
| 22 | + 2. Memory window |
| 23 | +- ppio-wins : number of requested ppio inbound windows |
| 24 | + default 1 inbound memory window is configured. |
| 25 | +- bus-range: PCI bus numbers covered |
| 26 | +- interrupt-controller: identifies the node as an interrupt controller |
| 27 | +- #interrupt-cells: specifies the number of cells needed to encode an |
| 28 | + interrupt source. The value must be 1. |
| 29 | +- interrupt-parent : phandle to the interrupt controller that |
| 30 | + it is attached to, it should be set to gic to point to |
| 31 | + ARM's Generic Interrupt Controller node in system DT. |
| 32 | +- interrupts: The interrupt line of the PCIe controller |
| 33 | + last cell of this field is set to 4 to |
| 34 | + denote it as IRQ_TYPE_LEVEL_HIGH type interrupt. |
| 35 | +- interrupt-map-mask, |
| 36 | + interrupt-map: standard PCI properties to define the mapping of the |
| 37 | + PCI interface to interrupt numbers. |
| 38 | +- ranges: ranges for the PCI memory regions (I/O space region is not |
| 39 | + supported by hardware) |
| 40 | + Please refer to the standard PCI bus binding document for a more |
| 41 | + detailed explanation |
| 42 | + |
| 43 | + |
| 44 | +Example: |
| 45 | +++++++++ |
| 46 | + pcie0: pcie@a0000000 { |
| 47 | + #address-cells = <3>; |
| 48 | + #size-cells = <2>; |
| 49 | + compatible = "mbvl,gpex40-pcie"; |
| 50 | + reg = <0xa0000000 0x00001000>, |
| 51 | + <0xb0000000 0x00010000>, |
| 52 | + <0xff000000 0x00200000>, |
| 53 | + <0xb0010000 0x00001000>; |
| 54 | + reg-names = "config_axi_slave", |
| 55 | + "csr_axi_slave", |
| 56 | + "gpio_slave", |
| 57 | + "apb_csr"; |
| 58 | + device_type = "pci"; |
| 59 | + apio-wins = <2>; |
| 60 | + ppio-wins = <1>; |
| 61 | + bus-range = <0x00000000 0x000000ff>; |
| 62 | + interrupt-controller; |
| 63 | + interrupt-parent = <&gic>; |
| 64 | + #interrupt-cells = <1>; |
| 65 | + interrupts = < 0 89 4 >; |
| 66 | + interrupt-map-mask = <0 0 0 7>; |
| 67 | + interrupt-map = <0 0 0 0 &pci_express 0>, |
| 68 | + <0 0 0 1 &pci_express 1>, |
| 69 | + <0 0 0 2 &pci_express 2>, |
| 70 | + <0 0 0 3 &pci_express 3>; |
| 71 | + ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>; |
| 72 | + |
| 73 | + }; |
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