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vaibhav92mpe
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cxl: Check if PSL data-cache is available before issue flush request
PSL9D doesn't have a data-cache that needs to be flushed before resetting the card. However when cxl tries to flush data-cache on such a card, it times-out as PSL_Control register never indicates flush operation complete due to missing data-cache. This is usually indicated in the kernel logs with this message: "WARNING: cache flush timed out" To fix this the patch checks PSL_Debug register CDC-Field(BIT:27) which indicates the absence of a data-cache and sets a flag 'no_data_cache' in 'struct cxl_native' to indicate this. When cxl_data_cache_flush() is called it checks the flag and if set bails out early without requesting a data-cache flush operation to the PSL. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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3 files changed

+27
-7
lines changed

3 files changed

+27
-7
lines changed

drivers/misc/cxl/cxl.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -369,6 +369,9 @@ static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
369369
#define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
370370
#define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
371371

372+
/****** CXL_PSL_DEBUG *****************************************************/
373+
#define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */
374+
372375
/****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
373376
#define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
374377
#define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
@@ -669,6 +672,7 @@ struct cxl_native {
669672
irq_hw_number_t err_hwirq;
670673
unsigned int err_virq;
671674
u64 ps_off;
675+
bool no_data_cache; /* set if no data cache on the card */
672676
const struct cxl_service_layer_ops *sl_ops;
673677
};
674678

drivers/misc/cxl/native.c

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -353,8 +353,17 @@ int cxl_data_cache_flush(struct cxl *adapter)
353353
u64 reg;
354354
unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
355355

356-
pr_devel("Flushing data cache\n");
356+
/*
357+
* Do a datacache flush only if datacache is available.
358+
* In case of PSL9D datacache absent hence flush operation.
359+
* would timeout.
360+
*/
361+
if (adapter->native->no_data_cache) {
362+
pr_devel("No PSL data cache. Ignoring cache flush req.\n");
363+
return 0;
364+
}
357365

366+
pr_devel("Flushing data cache\n");
358367
reg = cxl_p1_read(adapter, CXL_PSL_Control);
359368
reg |= CXL_PSL_Control_Fr;
360369
cxl_p1_write(adapter, CXL_PSL_Control, reg);

drivers/misc/cxl/pci.c

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -456,6 +456,7 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
456456
u64 chipid;
457457
u32 phb_index;
458458
u64 capp_unit_id;
459+
u64 psl_debug;
459460
int rc;
460461

461462
rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
@@ -510,6 +511,16 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
510511
cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
511512
}
512513

514+
/*
515+
* Check if PSL has data-cache. We need to flush adapter datacache
516+
* when as its about to be removed.
517+
*/
518+
psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
519+
if (psl_debug & CXL_PSL_DEBUG_CDC) {
520+
dev_dbg(&dev->dev, "No data-cache present\n");
521+
adapter->native->no_data_cache = true;
522+
}
523+
513524
return 0;
514525
}
515526

@@ -1448,10 +1459,8 @@ int cxl_pci_reset(struct cxl *adapter)
14481459

14491460
/*
14501461
* The adapter is about to be reset, so ignore errors.
1451-
* Not supported on P9 DD1
14521462
*/
1453-
if ((cxl_is_power8()) || (!(cxl_is_power9_dd1())))
1454-
cxl_data_cache_flush(adapter);
1463+
cxl_data_cache_flush(adapter);
14551464

14561465
/* pcie_warm_reset requests a fundamental pci reset which includes a
14571466
* PERST assert/deassert. PERST triggers a loading of the image
@@ -1934,10 +1943,8 @@ static void cxl_pci_remove_adapter(struct cxl *adapter)
19341943

19351944
/*
19361945
* Flush adapter datacache as its about to be removed.
1937-
* Not supported on P9 DD1.
19381946
*/
1939-
if ((cxl_is_power8()) || (!(cxl_is_power9_dd1())))
1940-
cxl_data_cache_flush(adapter);
1947+
cxl_data_cache_flush(adapter);
19411948

19421949
cxl_deconfigure_adapter(adapter);
19431950

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