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ickle
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drm/i915: Group the GT routines together in both code and vtable
Tidy up the routines for interacting with the GT (in particular the forcewake dance) which are scattered throughout the code in a single structure. v2: use wait_for_atomic for polling. v3: *really* use wait_for_atomic for polling. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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-80
lines changed

5 files changed

+73
-80
lines changed

‎drivers/gpu/drm/i915/i915_dma.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1548,6 +1548,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
15481548
}
15491549

15501550
intel_irq_init(dev);
1551+
intel_gt_init(dev);
15511552

15521553
/* Try to make sure MCHBAR is enabled before poking at it */
15531554
intel_setup_mchbar(dev);
@@ -1580,7 +1581,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
15801581
if (!IS_I945G(dev) && !IS_I945GM(dev))
15811582
pci_enable_msi(dev->pdev);
15821583

1583-
spin_lock_init(&dev_priv->gt_lock);
15841584
spin_lock_init(&dev_priv->irq_lock);
15851585
spin_lock_init(&dev_priv->error_lock);
15861586
spin_lock_init(&dev_priv->rps_lock);

‎drivers/gpu/drm/i915/i915_drv.c

Lines changed: 64 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232
#include "drm.h"
3333
#include "i915_drm.h"
3434
#include "i915_drv.h"
35+
#include "i915_trace.h"
3536
#include "intel_drv.h"
3637

3738
#include <linux/console.h>
@@ -432,36 +433,26 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
432433
return 1;
433434
}
434435

435-
void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
436+
static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
436437
{
437-
int count;
438-
439-
count = 0;
440-
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
441-
udelay(10);
438+
if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0, 500))
439+
DRM_ERROR("Force wake wait timed out\n");
442440

443441
I915_WRITE_NOTRACE(FORCEWAKE, 1);
444-
POSTING_READ(FORCEWAKE);
445442

446-
count = 0;
447-
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
448-
udelay(10);
443+
if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1), 500))
444+
DRM_ERROR("Force wake wait timed out\n");
449445
}
450446

451-
void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
447+
static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
452448
{
453-
int count;
454-
455-
count = 0;
456-
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
457-
udelay(10);
449+
if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0, 500))
450+
DRM_ERROR("Force wake wait timed out\n");
458451

459452
I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
460-
POSTING_READ(FORCEWAKE_MT);
461453

462-
count = 0;
463-
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
464-
udelay(10);
454+
if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1), 500))
455+
DRM_ERROR("Force wake wait timed out\n");
465456
}
466457

467458
/*
@@ -476,7 +467,7 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
476467

477468
spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
478469
if (dev_priv->forcewake_count++ == 0)
479-
dev_priv->display.force_wake_get(dev_priv);
470+
dev_priv->gt.force_wake_get(dev_priv);
480471
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
481472
}
482473

@@ -489,14 +480,14 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
489480
I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
490481
}
491482

492-
void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
483+
static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
493484
{
494485
I915_WRITE_NOTRACE(FORCEWAKE, 0);
495486
/* The below doubles as a POSTING_READ */
496487
gen6_gt_check_fifodbg(dev_priv);
497488
}
498489

499-
void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
490+
static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
500491
{
501492
I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
502493
/* The below doubles as a POSTING_READ */
@@ -512,7 +503,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
512503

513504
spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
514505
if (--dev_priv->forcewake_count == 0)
515-
dev_priv->display.force_wake_put(dev_priv);
506+
dev_priv->gt.force_wake_put(dev_priv);
516507
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
517508
}
518509

@@ -536,31 +527,67 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
536527
return ret;
537528
}
538529

539-
void vlv_force_wake_get(struct drm_i915_private *dev_priv)
530+
static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
540531
{
541-
int count;
542-
543-
count = 0;
544-
545532
/* Already awake? */
546533
if ((I915_READ(0x130094) & 0xa1) == 0xa1)
547534
return;
548535

549536
I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
550537
POSTING_READ(FORCEWAKE_VLV);
551538

552-
count = 0;
553-
while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
554-
udelay(10);
539+
if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 500))
540+
DRM_ERROR("Force wake wait timed out\n");
555541
}
556542

557-
void vlv_force_wake_put(struct drm_i915_private *dev_priv)
543+
static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
558544
{
559545
I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
560546
/* FIXME: confirm VLV behavior with Punit folks */
561547
POSTING_READ(FORCEWAKE_VLV);
562548
}
563549

550+
void intel_gt_init(struct drm_device *dev)
551+
{
552+
struct drm_i915_private *dev_priv = dev->dev_private;
553+
554+
spin_lock_init(&dev_priv->gt_lock);
555+
556+
if (IS_VALLEYVIEW(dev)) {
557+
dev_priv->gt.force_wake_get = vlv_force_wake_get;
558+
dev_priv->gt.force_wake_put = vlv_force_wake_put;
559+
} else if (INTEL_INFO(dev)->gen >= 6) {
560+
dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
561+
dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
562+
563+
/* IVB configs may use multi-threaded forcewake */
564+
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
565+
u32 ecobus;
566+
567+
/* A small trick here - if the bios hasn't configured
568+
* MT forcewake, and if the device is in RC6, then
569+
* force_wake_mt_get will not wake the device and the
570+
* ECOBUS read will return zero. Which will be
571+
* (correctly) interpreted by the test below as MT
572+
* forcewake being disabled.
573+
*/
574+
mutex_lock(&dev->struct_mutex);
575+
__gen6_gt_force_wake_mt_get(dev_priv);
576+
ecobus = I915_READ_NOTRACE(ECOBUS);
577+
__gen6_gt_force_wake_mt_put(dev_priv);
578+
mutex_unlock(&dev->struct_mutex);
579+
580+
if (ecobus & FORCEWAKE_MT_ENABLE) {
581+
DRM_DEBUG_KMS("Using MT version of forcewake\n");
582+
dev_priv->gt.force_wake_get =
583+
__gen6_gt_force_wake_mt_get;
584+
dev_priv->gt.force_wake_put =
585+
__gen6_gt_force_wake_mt_put;
586+
}
587+
}
588+
}
589+
}
590+
564591
static int i915_drm_freeze(struct drm_device *dev)
565592
{
566593
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -797,9 +824,9 @@ static int gen6_do_reset(struct drm_device *dev)
797824

798825
/* If reset with a user forcewake, try to restore, otherwise turn it off */
799826
if (dev_priv->forcewake_count)
800-
dev_priv->display.force_wake_get(dev_priv);
827+
dev_priv->gt.force_wake_get(dev_priv);
801828
else
802-
dev_priv->display.force_wake_put(dev_priv);
829+
dev_priv->gt.force_wake_put(dev_priv);
803830

804831
/* Restore fifo count */
805832
dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
@@ -1248,10 +1275,10 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
12481275
unsigned long irqflags; \
12491276
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
12501277
if (dev_priv->forcewake_count == 0) \
1251-
dev_priv->display.force_wake_get(dev_priv); \
1278+
dev_priv->gt.force_wake_get(dev_priv); \
12521279
val = read##y(dev_priv->regs + reg); \
12531280
if (dev_priv->forcewake_count == 0) \
1254-
dev_priv->display.force_wake_put(dev_priv); \
1281+
dev_priv->gt.force_wake_put(dev_priv); \
12551282
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
12561283
} else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
12571284
val = read##y(dev_priv->regs + reg + 0x180000); \

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -262,15 +262,18 @@ struct drm_i915_display_funcs {
262262
struct drm_i915_gem_object *obj);
263263
int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
264264
int x, int y);
265-
void (*force_wake_get)(struct drm_i915_private *dev_priv);
266-
void (*force_wake_put)(struct drm_i915_private *dev_priv);
267265
/* clock updates for mode set */
268266
/* cursor updates */
269267
/* render clock increase/decrease */
270268
/* display clock increase/decrease */
271269
/* pll clock increase/decrease */
272270
};
273271

272+
struct drm_i915_gt_funcs {
273+
void (*force_wake_get)(struct drm_i915_private *dev_priv);
274+
void (*force_wake_put)(struct drm_i915_private *dev_priv);
275+
};
276+
274277
struct intel_device_info {
275278
u8 gen;
276279
u8 is_mobile:1;
@@ -362,6 +365,8 @@ typedef struct drm_i915_private {
362365
int relative_constants_mode;
363366

364367
void __iomem *regs;
368+
369+
struct drm_i915_gt_funcs gt;
365370
/** gt_fifo_count and the subsequent register write are synchronized
366371
* with dev->struct_mutex. */
367372
unsigned gt_fifo_count;
@@ -1200,6 +1205,7 @@ void i915_hangcheck_elapsed(unsigned long data);
12001205
void i915_handle_error(struct drm_device *dev, bool wedged);
12011206

12021207
extern void intel_irq_init(struct drm_device *dev);
1208+
extern void intel_gt_init(struct drm_device *dev);
12031209

12041210
void i915_error_state_free(struct kref *error_ref);
12051211

@@ -1517,13 +1523,6 @@ extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
15171523
extern int intel_enable_rc6(const struct drm_device *dev);
15181524

15191525
extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1520-
extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1521-
extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1522-
extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1523-
extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1524-
1525-
extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
1526-
extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
15271526

15281527
/* overlay */
15291528
#ifdef CONFIG_DEBUG_FS

‎drivers/gpu/drm/i915/intel_display.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7013,9 +7013,6 @@ static void intel_init_display(struct drm_device *dev)
70137013
dev_priv->display.write_eld = ironlake_write_eld;
70147014
} else
70157015
dev_priv->display.update_wm = NULL;
7016-
} else if (IS_VALLEYVIEW(dev)) {
7017-
dev_priv->display.force_wake_get = vlv_force_wake_get;
7018-
dev_priv->display.force_wake_put = vlv_force_wake_put;
70197016
} else if (IS_G4X(dev)) {
70207017
dev_priv->display.write_eld = g4x_write_eld;
70217018
}

‎drivers/gpu/drm/i915/intel_pm.c

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -3765,34 +3765,6 @@ void intel_init_pm(struct drm_device *dev)
37653765

37663766
/* For FIFO watermark updates */
37673767
if (HAS_PCH_SPLIT(dev)) {
3768-
dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
3769-
dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
3770-
3771-
/* IVB configs may use multi-threaded forcewake */
3772-
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
3773-
u32 ecobus;
3774-
3775-
/* A small trick here - if the bios hasn't configured MT forcewake,
3776-
* and if the device is in RC6, then force_wake_mt_get will not wake
3777-
* the device and the ECOBUS read will return zero. Which will be
3778-
* (correctly) interpreted by the test below as MT forcewake being
3779-
* disabled.
3780-
*/
3781-
mutex_lock(&dev->struct_mutex);
3782-
__gen6_gt_force_wake_mt_get(dev_priv);
3783-
ecobus = I915_READ_NOTRACE(ECOBUS);
3784-
__gen6_gt_force_wake_mt_put(dev_priv);
3785-
mutex_unlock(&dev->struct_mutex);
3786-
3787-
if (ecobus & FORCEWAKE_MT_ENABLE) {
3788-
DRM_DEBUG_KMS("Using MT version of forcewake\n");
3789-
dev_priv->display.force_wake_get =
3790-
__gen6_gt_force_wake_mt_get;
3791-
dev_priv->display.force_wake_put =
3792-
__gen6_gt_force_wake_mt_put;
3793-
}
3794-
}
3795-
37963768
if (HAS_PCH_IBX(dev))
37973769
dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
37983770
else if (HAS_PCH_CPT(dev))
@@ -3848,8 +3820,6 @@ void intel_init_pm(struct drm_device *dev)
38483820
dev_priv->display.update_wm = valleyview_update_wm;
38493821
dev_priv->display.init_clock_gating =
38503822
valleyview_init_clock_gating;
3851-
dev_priv->display.force_wake_get = vlv_force_wake_get;
3852-
dev_priv->display.force_wake_put = vlv_force_wake_put;
38533823
} else if (IS_PINEVIEW(dev)) {
38543824
if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
38553825
dev_priv->is_ddr3,

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