Skip to content

Commit 999dcbe

Browse files
torvaldstorvalds
committed
Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "The irq departement proudly presents: - A rework of the core infrastructure to optimally spread interrupt for multiqueue devices. The first version was a bit naive and failed to take thread siblings and other details into account. Developed in cooperation with Christoph and Keith. - Proper delegation of softirqs to ksoftirqd, so if ksoftirqd is active then no further softirq processsing on interrupt return happens. Otherwise we try to delegate and still run another batch of network packets in the irq return path, which then tries to delegate to ksoftirqd ..... - A proper machine parseable sysfs based alternative for /proc/interrupts. - ACPI support for the GICV3-ITS and ARM interrupt remapping - Two new irq chips from the ARM SoC zoo: STM32-EXTI and MVEBU-PIC - A new irq chip for the JCore (SuperH) - The usual pile of small fixlets in core and irqchip drivers" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (42 commits) softirq: Let ksoftirqd do its job genirq: Make function __irq_do_set_handler() static ARM/dts: Add EXTI controller node to stm32f429 ARM/STM32: Select external interrupts controller drivers/irqchip: Add STM32 external interrupts support Documentation/dt-bindings: Document STM32 EXTI controller bindings irqchip/mips-gic: Use for_each_set_bit to iterate over local IRQs pci/msi: Retrieve affinity for a vector genirq/affinity: Remove old irq spread infrastructure genirq/msi: Switch to new irq spreading infrastructure genirq/affinity: Provide smarter irq spreading infrastructure genirq/msi: Add cpumask allocation to alloc_msi_entry genirq: Expose interrupt information through sysfs irqchip/gicv3-its: Use MADT ITS subtable to do PCI/MSI domain initialization irqchip/gicv3-its: Factor out PCI-MSI part that might be reused for ACPI irqchip/gicv3-its: Probe ITS in the ACPI way irqchip/gicv3-its: Refactor ITS DT init code to prepare for ACPI irqchip/gicv3-its: Cleanup for ITS domain initialization PCI/MSI: Setup MSI domain on a per-device basis using IORT ACPI table ACPI: Add new IORT functions to support MSI domain handling ...
2 parents 5e1b834 + 4cd13c2 commit 999dcbe

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

46 files changed

+1924
-281
lines changed

‎Documentation/ABI/testing/sysfs-kernel-irq

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
What: /sys/kernel/irq
2+
Date: September 2016
3+
KernelVersion: 4.9
4+
Contact: Craig Gallek <kraig@google.com>
5+
Description: Directory containing information about the system's IRQs.
6+
Specifically, data from the associated struct irq_desc.
7+
The information here is similar to that in /proc/interrupts
8+
but in a more machine-friendly format. This directory contains
9+
one subdirectory for each Linux IRQ number.
10+
11+
What: /sys/kernel/irq/<irq>/actions
12+
Date: September 2016
13+
KernelVersion: 4.9
14+
Contact: Craig Gallek <kraig@google.com>
15+
Description: The IRQ action chain. A comma-separated list of zero or more
16+
device names associated with this interrupt.
17+
18+
What: /sys/kernel/irq/<irq>/chip_name
19+
Date: September 2016
20+
KernelVersion: 4.9
21+
Contact: Craig Gallek <kraig@google.com>
22+
Description: Human-readable chip name supplied by the associated device
23+
driver.
24+
25+
What: /sys/kernel/irq/<irq>/hwirq
26+
Date: September 2016
27+
KernelVersion: 4.9
28+
Contact: Craig Gallek <kraig@google.com>
29+
Description: When interrupt translation domains are used, this file contains
30+
the underlying hardware IRQ number used for this Linux IRQ.
31+
32+
What: /sys/kernel/irq/<irq>/name
33+
Date: September 2016
34+
KernelVersion: 4.9
35+
Contact: Craig Gallek <kraig@google.com>
36+
Description: Human-readable flow handler name as defined by the irq chip
37+
driver.
38+
39+
What: /sys/kernel/irq/<irq>/per_cpu_count
40+
Date: September 2016
41+
KernelVersion: 4.9
42+
Contact: Craig Gallek <kraig@google.com>
43+
Description: The number of times the interrupt has fired since boot. This
44+
is a comma-separated list of counters; one per CPU in CPU id
45+
order. NOTE: This file consistently shows counters for all
46+
CPU ids. This differs from the behavior of /proc/interrupts
47+
which only shows counters for online CPUs.
48+
49+
What: /sys/kernel/irq/<irq>/type
50+
Date: September 2016
51+
KernelVersion: 4.9
52+
Contact: Craig Gallek <kraig@google.com>
53+
Description: The type of the interrupt. Either the string 'level' or 'edge'.

‎Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
J-Core Advanced Interrupt Controller
2+
3+
Required properties:
4+
5+
- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
6+
with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
7+
the "aic2" core with 64 interrupts.
8+
9+
- reg: Memory region(s) for configuration. For SMP, there should be one
10+
region per cpu, indexed by the sequential, zero-based hardware cpu
11+
number.
12+
13+
- interrupt-controller: Identifies the node as an interrupt controller
14+
15+
- #interrupt-cells: Specifies the number of cells needed to encode an
16+
interrupt source. The value shall be 1.
17+
18+
19+
Example:
20+
21+
aic: interrupt-controller@200 {
22+
compatible = "jcore,aic2";
23+
reg = < 0x200 0x30 0x500 0x30 >;
24+
interrupt-controller;
25+
#interrupt-cells = <1>;
26+
};

‎Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
Marvell Armada 7K/8K PIC Interrupt controller
2+
---------------------------------------------
3+
4+
This is the Device Tree binding for the PIC, a secondary interrupt
5+
controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
6+
typically connected to the GIC as the primary interrupt controller.
7+
8+
Required properties:
9+
- compatible: should be "marvell,armada-8k-pic"
10+
- interrupt-controller: identifies the node as an interrupt controller
11+
- #interrupt-cells: the number of cells to define interrupts on this
12+
controller. Should be 1
13+
- reg: the register area for the PIC interrupt controller
14+
- interrupts: the interrupt to the primary interrupt controller,
15+
typically the GIC
16+
17+
Example:
18+
19+
pic: interrupt-controller@3f0100 {
20+
compatible = "marvell,armada-8k-pic";
21+
reg = <0x3f0100 0x10>;
22+
#interrupt-cells = <1>;
23+
interrupt-controller;
24+
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
25+
};

‎Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ Required properties:
3131
Example:
3232

3333
odmi: odmi@300000 {
34-
compatible = "marvell,ap806-odm-controller",
34+
compatible = "marvell,ap806-odmi-controller",
3535
"marvell,odmi-controller";
3636
interrupt-controller;
3737
msi-controller;

‎Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
STM32 External Interrupt Controller
2+
3+
Required properties:
4+
5+
- compatible: Should be "st,stm32-exti"
6+
- reg: Specifies base physical address and size of the registers
7+
- interrupt-controller: Indentifies the node as an interrupt controller
8+
- #interrupt-cells: Specifies the number of cells to encode an interrupt
9+
specifier, shall be 2
10+
- interrupts: interrupts references to primary interrupt controller
11+
12+
Example:
13+
14+
exti: interrupt-controller@40013c00 {
15+
compatible = "st,stm32-exti";
16+
interrupt-controller;
17+
#interrupt-cells = <2>;
18+
reg = <0x40013C00 0x400>;
19+
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
20+
};

‎arch/arm/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -879,6 +879,7 @@ config ARCH_STM32
879879
select CLKSRC_STM32
880880
select PINCTRL
881881
select RESET_CONTROLLER
882+
select STM32_EXTI
882883
help
883884
Support for STMicroelectronics STM32 processors.
884885

‎arch/arm/boot/dts/stm32f429.dtsi

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,14 @@
176176
reg = <0x40013800 0x400>;
177177
};
178178

179+
exti: interrupt-controller@40013c00 {
180+
compatible = "st,stm32-exti";
181+
interrupt-controller;
182+
#interrupt-cells = <2>;
183+
reg = <0x40013C00 0x400>;
184+
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
185+
};
186+
179187
pin-controller {
180188
#address-cells = <1>;
181189
#size-cells = <1>;

‎arch/arm/include/asm/arch_gicv3.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
#define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4)
3535
#define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
3636
#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
37+
#define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3)
3738

3839
#define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5)
3940

@@ -157,6 +158,11 @@ static inline void gic_write_sre(u32 val)
157158
isb();
158159
}
159160

161+
static inline void gic_write_bpr1(u32 val)
162+
{
163+
asm volatile("mcr " __stringify(ICC_BPR1) : : "r" (val));
164+
}
165+
160166
/*
161167
* Even in 32bit systems that use LPAE, there is no guarantee that the I/O
162168
* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't

‎arch/arm64/Kconfig.platforms

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,7 @@ config ARCH_MVEBU
9393
select ARMADA_CP110_SYSCON
9494
select ARMADA_37XX_CLK
9595
select MVEBU_ODMI
96+
select MVEBU_PIC
9697
help
9798
This enables support for Marvell EBU familly, including:
9899
- Armada 3700 SoC Family

‎arch/arm64/include/asm/arch_gicv3.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
2929
#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
3030
#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
31+
#define ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
3132

3233
#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
3334

@@ -165,6 +166,11 @@ static inline void gic_write_sre(u32 val)
165166
isb();
166167
}
167168

169+
static inline void gic_write_bpr1(u32 val)
170+
{
171+
asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
172+
}
173+
168174
#define gic_read_typer(c) readq_relaxed(c)
169175
#define gic_write_irouter(v, c) writeq_relaxed(v, c)
170176

‎drivers/acpi/Kconfig

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -523,4 +523,8 @@ config ACPI_CONFIGFS
523523
userspace. The configurable ACPI groups will be visible under
524524
/config/acpi, assuming configfs is mounted under /config.
525525

526+
if ARM64
527+
source "drivers/acpi/arm64/Kconfig"
528+
endif
529+
526530
endif # ACPI

‎drivers/acpi/Makefile

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,3 +106,5 @@ obj-$(CONFIG_ACPI_CONFIGFS) += acpi_configfs.o
106106

107107
video-objs += acpi_video.o video_detect.o
108108
obj-y += dptf/
109+
110+
obj-$(CONFIG_ARM64) += arm64/

‎drivers/acpi/arm64/Kconfig

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
#
2+
# ACPI Configuration for ARM64
3+
#
4+
5+
config ACPI_IORT
6+
bool

‎drivers/acpi/arm64/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
obj-$(CONFIG_ACPI_IORT) += iort.o

0 commit comments

Comments
 (0)