@@ -788,17 +788,16 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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{
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if (hw < 32 ) {
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irq_set_percpu_devid (irq );
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- irq_set_chip_and_handler ( irq , & gic_chip ,
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- handle_percpu_devid_irq );
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+ irq_domain_set_info ( d , irq , hw , & gic_chip , d -> host_data ,
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+ handle_percpu_devid_irq , NULL , NULL );
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set_irq_flags (irq , IRQF_VALID | IRQF_NOAUTOEN );
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} else {
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- irq_set_chip_and_handler ( irq , & gic_chip ,
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- handle_fasteoi_irq );
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+ irq_domain_set_info ( d , irq , hw , & gic_chip , d -> host_data ,
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+ handle_fasteoi_irq , NULL , NULL );
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set_irq_flags (irq , IRQF_VALID | IRQF_PROBE );
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gic_routable_irq_domain_ops -> map (d , irq , hw );
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}
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- irq_set_chip_data (irq , d -> host_data );
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return 0 ;
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}
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@@ -858,6 +857,31 @@ static struct notifier_block gic_cpu_notifier = {
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};
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#endif
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+ static int gic_irq_domain_alloc (struct irq_domain * domain , unsigned int virq ,
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+ unsigned int nr_irqs , void * arg )
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+ {
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+ int i , ret ;
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+ irq_hw_number_t hwirq ;
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+ unsigned int type = IRQ_TYPE_NONE ;
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+ struct of_phandle_args * irq_data = arg ;
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+
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+ ret = gic_irq_domain_xlate (domain , irq_data -> np , irq_data -> args ,
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+ irq_data -> args_count , & hwirq , & type );
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+ if (ret )
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+ return ret ;
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+
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+ for (i = 0 ; i < nr_irqs ; i ++ )
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+ gic_irq_domain_map (domain , virq + i , hwirq + i );
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+
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+ return 0 ;
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+ }
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+
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+ static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
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+ .xlate = gic_irq_domain_xlate ,
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+ .alloc = gic_irq_domain_alloc ,
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+ .free = irq_domain_free_irqs_top ,
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+ };
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+
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static const struct irq_domain_ops gic_irq_domain_ops = {
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.map = gic_irq_domain_map ,
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.unmap = gic_irq_domain_unmap ,
@@ -947,18 +971,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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for (i = 0 ; i < NR_GIC_CPU_IF ; i ++ )
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gic_cpu_map [i ] = 0xff ;
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- /*
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- * For primary GICs, skip over SGIs.
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- * For secondary GICs, skip over PPIs, too.
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- */
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- if (gic_nr == 0 && (irq_start & 31 ) > 0 ) {
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- hwirq_base = 16 ;
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- if (irq_start != -1 )
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- irq_start = (irq_start & ~31 ) + 16 ;
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- } else {
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- hwirq_base = 32 ;
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- }
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-
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/*
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* Find out how many interrupts are supported.
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* The GIC only supports up to 1020 interrupt sources.
@@ -969,10 +981,31 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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gic_irqs = 1020 ;
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gic -> gic_irqs = gic_irqs ;
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- gic_irqs -= hwirq_base ; /* calculate # of irqs to allocate */
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+ if (node ) { /* DT case */
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+ const struct irq_domain_ops * ops = & gic_irq_domain_hierarchy_ops ;
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+
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+ if (!of_property_read_u32 (node , "arm,routable-irqs" ,
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+ & nr_routable_irqs )) {
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+ ops = & gic_irq_domain_ops ;
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+ gic_irqs = nr_routable_irqs ;
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+ }
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+
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+ gic -> domain = irq_domain_add_linear (node , gic_irqs , ops , gic );
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+ } else { /* Non-DT case */
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+ /*
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+ * For primary GICs, skip over SGIs.
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+ * For secondary GICs, skip over PPIs, too.
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+ */
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+ if (gic_nr == 0 && (irq_start & 31 ) > 0 ) {
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+ hwirq_base = 16 ;
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+ if (irq_start != -1 )
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+ irq_start = (irq_start & ~31 ) + 16 ;
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+ } else {
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+ hwirq_base = 32 ;
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+ }
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+
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+ gic_irqs -= hwirq_base ; /* calculate # of irqs to allocate */
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- if (of_property_read_u32 (node , "arm,routable-irqs" ,
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- & nr_routable_irqs )) {
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irq_base = irq_alloc_descs (irq_start , 16 , gic_irqs ,
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numa_node_id ());
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if (IS_ERR_VALUE (irq_base )) {
@@ -983,10 +1016,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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gic -> domain = irq_domain_add_legacy (node , gic_irqs , irq_base ,
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hwirq_base , & gic_irq_domain_ops , gic );
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- } else {
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- gic -> domain = irq_domain_add_linear (node , nr_routable_irqs ,
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- & gic_irq_domain_ops ,
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- gic );
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}
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if (WARN_ON (!gic -> domain ))
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