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baruchsiachdlezcano
baruchsiach
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clocksource: Driver for Conexant Digicolor SoC timer
Add clocksource driver to the Conexant CX92755 SoC, part of the Digicolor SoCs series. Hardware provides 8 timers, A to H. Timer A is dedicated to a future watchdog driver so we don't use it here. Use timer B for sched_clock, and timer C for clock_event. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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‎drivers/clocksource/Kconfig

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@@ -18,6 +18,9 @@ config CLKBLD_I8253
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config CLKSRC_MMIO
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bool
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config DIGICOLOR_TIMER
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bool
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config DW_APB_TIMER
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bool
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‎drivers/clocksource/Makefile

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@@ -10,6 +10,7 @@ obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
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obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
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obj-$(CONFIG_CLKBLD_I8253) += i8253.o
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obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
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obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
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obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
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obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
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obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o

‎drivers/clocksource/timer-digicolor.c

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/*
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* Conexant Digicolor timer driver
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*
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* Author: Baruch Siach <baruch@tkos.co.il>
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*
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* Copyright (C) 2014 Paradox Innovation Ltd.
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*
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* Based on:
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* Allwinner SoCs hstimer driver
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*
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* Copyright (C) 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/*
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* Conexant Digicolor SoCs have 8 configurable timers, named from "Timer A" to
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* "Timer H". Timer A is the only one with watchdog support, so it is dedicated
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* to the watchdog driver. This driver uses Timer B for sched_clock(), and
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* Timer C for clockevents.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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enum {
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TIMER_A,
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TIMER_B,
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TIMER_C,
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TIMER_D,
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TIMER_E,
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TIMER_F,
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TIMER_G,
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TIMER_H,
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};
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#define CONTROL(t) ((t)*8)
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#define COUNT(t) ((t)*8 + 4)
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#define CONTROL_DISABLE 0
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#define CONTROL_ENABLE BIT(0)
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#define CONTROL_MODE(m) ((m) << 4)
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#define CONTROL_MODE_ONESHOT CONTROL_MODE(1)
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#define CONTROL_MODE_PERIODIC CONTROL_MODE(2)
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struct digicolor_timer {
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struct clock_event_device ce;
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void __iomem *base;
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u32 ticks_per_jiffy;
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int timer_id; /* one of TIMER_* */
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};
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struct digicolor_timer *dc_timer(struct clock_event_device *ce)
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{
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return container_of(ce, struct digicolor_timer, ce);
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}
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static inline void dc_timer_disable(struct clock_event_device *ce)
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{
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struct digicolor_timer *dt = dc_timer(ce);
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writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id));
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}
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static inline void dc_timer_enable(struct clock_event_device *ce, u32 mode)
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{
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struct digicolor_timer *dt = dc_timer(ce);
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writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id));
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}
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static inline void dc_timer_set_count(struct clock_event_device *ce,
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unsigned long count)
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{
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struct digicolor_timer *dt = dc_timer(ce);
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writel(count, dt->base + COUNT(dt->timer_id));
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}
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static void digicolor_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *ce)
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{
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struct digicolor_timer *dt = dc_timer(ce);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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dc_timer_disable(ce);
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dc_timer_set_count(ce, dt->ticks_per_jiffy);
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dc_timer_enable(ce, CONTROL_MODE_PERIODIC);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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dc_timer_disable(ce);
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dc_timer_enable(ce, CONTROL_MODE_ONESHOT);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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dc_timer_disable(ce);
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break;
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}
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}
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static int digicolor_clkevt_next_event(unsigned long evt,
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struct clock_event_device *ce)
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{
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dc_timer_disable(ce);
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dc_timer_set_count(ce, evt);
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dc_timer_enable(ce, CONTROL_MODE_ONESHOT);
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return 0;
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}
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static struct digicolor_timer dc_timer_dev = {
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.ce = {
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.name = "digicolor_tick",
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.rating = 340,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = digicolor_clkevt_mode,
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.set_next_event = digicolor_clkevt_next_event,
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},
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.timer_id = TIMER_C,
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};
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static irqreturn_t digicolor_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static u64 digicolor_timer_sched_read(void)
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{
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return ~readl(dc_timer_dev.base + COUNT(TIMER_B));
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}
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static void __init digicolor_timer_init(struct device_node *node)
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{
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unsigned long rate;
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struct clk *clk;
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int ret, irq;
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/*
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* timer registers are shared with the watchdog timer;
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* don't map exclusively
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*/
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dc_timer_dev.base = of_iomap(node, 0);
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if (!dc_timer_dev.base) {
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pr_err("Can't map registers");
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return;
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}
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irq = irq_of_parse_and_map(node, dc_timer_dev.timer_id);
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if (irq <= 0) {
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pr_err("Can't parse IRQ");
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return;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("Can't get timer clock");
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return;
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}
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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dc_timer_dev.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
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writeb(CONTROL_DISABLE, dc_timer_dev.base + CONTROL(TIMER_B));
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writel(UINT_MAX, dc_timer_dev.base + COUNT(TIMER_B));
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writeb(CONTROL_ENABLE, dc_timer_dev.base + CONTROL(TIMER_B));
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sched_clock_register(digicolor_timer_sched_read, 32, rate);
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clocksource_mmio_init(dc_timer_dev.base + COUNT(TIMER_B), node->name,
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rate, 340, 32, clocksource_mmio_readl_down);
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ret = request_irq(irq, digicolor_timer_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL, "digicolor_timerC",
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&dc_timer_dev.ce);
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if (ret)
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pr_warn("request of timer irq %d failed (%d)\n", irq, ret);
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dc_timer_dev.ce.cpumask = cpu_possible_mask;
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dc_timer_dev.ce.irq = irq;
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clockevents_config_and_register(&dc_timer_dev.ce, rate, 0, 0xffffffff);
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}
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CLOCKSOURCE_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer",
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digicolor_timer_init);

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