ethernet0 = &gmac2io;

ethernet1 = &gmac2phy;

gmac2phy: ethernet@ff550000 {

compatible = "rockchip,rk3328-gmac";

reg = <0x0 0xff550000 0x0 0x10000>;

rockchip,grf = <&grf>;

interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

interrupt-names = "macirq";

clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,

<&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,

<&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,

<&cru SCLK_MAC2PHY_OUT>;

clock-names = "stmmaceth", "mac_clk_rx",

"mac_clk_tx", "clk_mac_ref",

"aclk_mac", "pclk_mac",

"clk_macphy";

resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;

reset-names = "stmmaceth", "mac-phy";

phy-mode = "rmii";

phy-handle = <&phy>;

status = "disabled";

mdio {

compatible = "snps,dwmac-mdio";

#address-cells = <1>;

#size-cells = <0>;

phy: phy@0 {

compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";

reg = <0>;

clocks = <&cru SCLK_MAC2PHY_OUT>;

resets = <&cru SRST_MACPHY>;

pinctrl-names = "default";

pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;

phy-is-integrated;

};

};

};