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Merge branch 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more fixes and cleanups for 4.6: - DCE code cleanups - HDP flush/invalidation fixes - GPUVM fixes - switch to drm_vblank_[on|off] - PX fixes - misc bug fixes * 'drm-next-4.6' of git://people.freedesktop.org/~agd5f/linux: (50 commits) drm/amdgpu: split pipeline sync out of SDMA vm_flush() as well drm/amdgpu: Revert "add mutex for ba_va->valids/invalids" drm/amdgpu: Revert "add lock for interval tree in vm" drm/amdgpu: Revert "add spin lock to protect freed list in vm (v3)" drm/amdgpu: reserve the PD during unmap and remove drm/amdgpu: Fix two bugs in amdgpu_vm_bo_split_mapping drm/radeon: Don't drop DP 2.7 Ghz link setup on some cards. MAINTAINERS: update radeon entry to include amdgpu as well drm/amdgpu: disable runtime pm on PX laptops without dGPU power control drm/radeon: disable runtime pm on PX laptops without dGPU power control drm/amd/amdgpu: Fix indentation in do_set_base() (DCEv8) drm/amd/amdgpu: make afmt_init cleanup if alloc fails (DCEv8) drm/amd/amdgpu: Move config init flag to bottom of sw_init (DCEv8) drm/amd/amdgpu: Don't proceed into audio_fini if audio is disabled (DCEv8) drm/amd/amdgpu: Fix identation in do_set_base() (DCEv10) drm/amd/amdgpu: Make afmt_init cleanup if alloc fails (DCEv10) drm/amd/amdgpu: Move initialized flag to bottom of sw_init (DCEv10) drm/amd/amdgpu: Don't proceed in audio_fini if disabled (DCEv10) drm/amd/amdgpu: Fix indentation in dce_v11_0_crtc_do_set_base() drm/amd/amdgpu: Make afmt_init() cleanup if alloc fails (DCEv11) ...
2 parents 70a09f3 + 00b7c4f commit 9f443bf

36 files changed

+741
-312
lines changed

‎MAINTAINERS

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3710,14 +3710,16 @@ F: drivers/gpu/vga/
37103710
F: include/drm/
37113711
F: include/uapi/drm/
37123712

3713-
RADEON DRM DRIVERS
3713+
RADEON and AMDGPU DRM DRIVERS
37143714
M: Alex Deucher <alexander.deucher@amd.com>
37153715
M: Christian König <christian.koenig@amd.com>
37163716
L: dri-devel@lists.freedesktop.org
37173717
T: git git://people.freedesktop.org/~agd5f/linux
37183718
S: Supported
37193719
F: drivers/gpu/drm/radeon/
37203720
F: include/uapi/drm/radeon*
3721+
F: drivers/gpu/drm/amd/
3722+
F: include/uapi/drm/amdgpu*
37213723

37223724
DRM PANEL DRIVERS
37233725
M: Thierry Reding <thierry.reding@gmail.com>

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 27 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -287,9 +287,11 @@ struct amdgpu_ring_funcs {
287287
struct amdgpu_ib *ib);
288288
void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
289289
uint64_t seq, unsigned flags);
290+
void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
290291
void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
291292
uint64_t pd_addr);
292293
void (*emit_hdp_flush)(struct amdgpu_ring *ring);
294+
void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
293295
void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
294296
uint32_t gds_base, uint32_t gds_size,
295297
uint32_t gws_base, uint32_t gws_size,
@@ -369,9 +371,6 @@ struct amdgpu_fence {
369371
struct amdgpu_ring *ring;
370372
uint64_t seq;
371373

372-
/* filp or special value for fence creator */
373-
void *owner;
374-
375374
wait_queue_t fence_wake;
376375
};
377376

@@ -392,8 +391,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
392391
unsigned irq_type);
393392
void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
394393
void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
395-
int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
396-
struct amdgpu_fence **fence);
394+
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
397395
void amdgpu_fence_process(struct amdgpu_ring *ring);
398396
int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
399397
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
@@ -434,6 +432,8 @@ struct amdgpu_bo_list_entry {
434432
struct ttm_validate_buffer tv;
435433
struct amdgpu_bo_va *bo_va;
436434
uint32_t priority;
435+
struct page **user_pages;
436+
int user_invalidated;
437437
};
438438

439439
struct amdgpu_bo_va_mapping {
@@ -445,7 +445,6 @@ struct amdgpu_bo_va_mapping {
445445

446446
/* bo virtual addresses in a specific vm */
447447
struct amdgpu_bo_va {
448-
struct mutex mutex;
449448
/* protected by bo being reserved */
450449
struct list_head bo_list;
451450
struct fence *last_pt_update;
@@ -596,6 +595,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
596595
struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
597596
int amdgpu_sync_wait(struct amdgpu_sync *sync);
598597
void amdgpu_sync_free(struct amdgpu_sync *sync);
598+
int amdgpu_sync_init(void);
599+
void amdgpu_sync_fini(void);
599600

600601
/*
601602
* GART structures, functions & helpers
@@ -726,7 +727,7 @@ struct amdgpu_ib {
726727
uint32_t length_dw;
727728
uint64_t gpu_addr;
728729
uint32_t *ptr;
729-
struct amdgpu_fence *fence;
730+
struct fence *fence;
730731
struct amdgpu_user_fence *user;
731732
struct amdgpu_vm *vm;
732733
unsigned vm_id;
@@ -845,7 +846,6 @@ struct amdgpu_vm_id {
845846

846847
struct amdgpu_vm {
847848
/* tree of virtual addresses mapped */
848-
spinlock_t it_lock;
849849
struct rb_root va;
850850

851851
/* protecting invalidated */
@@ -882,6 +882,13 @@ struct amdgpu_vm_manager_id {
882882
struct list_head list;
883883
struct fence *active;
884884
atomic_long_t owner;
885+
886+
uint32_t gds_base;
887+
uint32_t gds_size;
888+
uint32_t gws_base;
889+
uint32_t gws_size;
890+
uint32_t oa_base;
891+
uint32_t oa_size;
885892
};
886893

887894
struct amdgpu_vm_manager {
@@ -917,8 +924,11 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
917924
struct amdgpu_sync *sync, struct fence *fence,
918925
unsigned *vm_id, uint64_t *vm_pd_addr);
919926
void amdgpu_vm_flush(struct amdgpu_ring *ring,
920-
unsigned vmid,
921-
uint64_t pd_addr);
927+
unsigned vm_id, uint64_t pd_addr,
928+
uint32_t gds_base, uint32_t gds_size,
929+
uint32_t gws_base, uint32_t gws_size,
930+
uint32_t oa_base, uint32_t oa_size);
931+
void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
922932
uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
923933
int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
924934
struct amdgpu_vm *vm);
@@ -1006,7 +1016,7 @@ struct amdgpu_bo_list {
10061016
struct amdgpu_bo *gds_obj;
10071017
struct amdgpu_bo *gws_obj;
10081018
struct amdgpu_bo *oa_obj;
1009-
bool has_userptr;
1019+
unsigned first_userptr;
10101020
unsigned num_entries;
10111021
struct amdgpu_bo_list_entry *array;
10121022
};
@@ -1135,8 +1145,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
11351145
unsigned size, struct amdgpu_ib *ib);
11361146
void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
11371147
int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1138-
struct amdgpu_ib *ib, void *owner,
1139-
struct fence *last_vm_update,
1148+
struct amdgpu_ib *ib, struct fence *last_vm_update,
11401149
struct fence **f);
11411150
int amdgpu_ib_pool_init(struct amdgpu_device *adev);
11421151
void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
@@ -2012,7 +2021,6 @@ struct amdgpu_device {
20122021
struct amdgpu_sdma sdma;
20132022

20142023
/* uvd */
2015-
bool has_uvd;
20162024
struct amdgpu_uvd uvd;
20172025

20182026
/* vce */
@@ -2186,10 +2194,12 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
21862194
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
21872195
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
21882196
#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2197+
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
21892198
#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
21902199
#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
21912200
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
21922201
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2202+
#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
21932203
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
21942204
#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
21952205
#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
@@ -2314,12 +2324,15 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
23142324
struct amdgpu_ring **out_ring);
23152325
void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
23162326
bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2327+
int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
23172328
int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
23182329
uint32_t flags);
23192330
bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
23202331
struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
23212332
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
23222333
unsigned long end);
2334+
bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2335+
int *last_invalidated);
23232336
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
23242337
uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
23252338
struct ttm_mem_reg *mem);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,10 @@ bool amdgpu_has_atpx(void) {
6363
return amdgpu_atpx_priv.atpx_detected;
6464
}
6565

66+
bool amdgpu_has_atpx_dgpu_power_cntl(void) {
67+
return amdgpu_atpx_priv.atpx.functions.power_cntl;
68+
}
69+
6670
/**
6771
* amdgpu_atpx_call - call an ATPX method
6872
*
@@ -142,10 +146,6 @@ static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mas
142146
*/
143147
static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
144148
{
145-
/* make sure required functions are enabled */
146-
/* dGPU power control is required */
147-
atpx->functions.power_cntl = true;
148-
149149
if (atpx->functions.px_params) {
150150
union acpi_object *info;
151151
struct atpx_px_params output;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c

Lines changed: 16 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
9191
struct amdgpu_bo *gws_obj = adev->gds.gws_gfx_bo;
9292
struct amdgpu_bo *oa_obj = adev->gds.oa_gfx_bo;
9393

94-
bool has_userptr = false;
94+
unsigned last_entry = 0, first_userptr = num_entries;
9595
unsigned i;
9696
int r;
9797

@@ -101,8 +101,9 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
101101
memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry));
102102

103103
for (i = 0; i < num_entries; ++i) {
104-
struct amdgpu_bo_list_entry *entry = &array[i];
104+
struct amdgpu_bo_list_entry *entry;
105105
struct drm_gem_object *gobj;
106+
struct amdgpu_bo *bo;
106107
struct mm_struct *usermm;
107108

108109
gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle);
@@ -111,19 +112,24 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
111112
goto error_free;
112113
}
113114

114-
entry->robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
115+
bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
115116
drm_gem_object_unreference_unlocked(gobj);
116-
entry->priority = min(info[i].bo_priority,
117-
AMDGPU_BO_LIST_MAX_PRIORITY);
118-
usermm = amdgpu_ttm_tt_get_usermm(entry->robj->tbo.ttm);
117+
118+
usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
119119
if (usermm) {
120120
if (usermm != current->mm) {
121-
amdgpu_bo_unref(&entry->robj);
121+
amdgpu_bo_unref(&bo);
122122
r = -EPERM;
123123
goto error_free;
124124
}
125-
has_userptr = true;
125+
entry = &array[--first_userptr];
126+
} else {
127+
entry = &array[last_entry++];
126128
}
129+
130+
entry->robj = bo;
131+
entry->priority = min(info[i].bo_priority,
132+
AMDGPU_BO_LIST_MAX_PRIORITY);
127133
entry->tv.bo = &entry->robj->tbo;
128134
entry->tv.shared = true;
129135

@@ -145,7 +151,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
145151
list->gds_obj = gds_obj;
146152
list->gws_obj = gws_obj;
147153
list->oa_obj = oa_obj;
148-
list->has_userptr = has_userptr;
154+
list->first_userptr = first_userptr;
149155
list->array = array;
150156
list->num_entries = num_entries;
151157

@@ -194,6 +200,7 @@ void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
194200

195201
list_add_tail(&list->array[i].tv.head,
196202
&bucket[priority]);
203+
list->array[i].user_pages = NULL;
197204
}
198205

199206
/* Connect the sorted buckets in the output list. */

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