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Cristina Ciocanlinusw
Cristina Ciocan
authored and
linusw
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pinctrl: baytrail: Update irq chip operations
This patch updates the irq chip implementation in order to interact with the pin control chip model: the chip contains reference to SOC data and pin/group/community information is retrieved through the SOC reference. Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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‎drivers/pinctrl/intel/pinctrl-baytrail.c

Lines changed: 51 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1120,41 +1120,6 @@ static int byt_gpio_request(struct gpio_chip *chip, unsigned int offset)
11201120
return 0;
11211121
}
11221122

1123-
static int byt_irq_type(struct irq_data *d, unsigned type)
1124-
{
1125-
struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1126-
u32 offset = irqd_to_hwirq(d);
1127-
u32 value;
1128-
unsigned long flags;
1129-
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1130-
1131-
if (offset >= vg->chip.ngpio)
1132-
return -EINVAL;
1133-
1134-
raw_spin_lock_irqsave(&vg->lock, flags);
1135-
value = readl(reg);
1136-
1137-
WARN(value & BYT_DIRECT_IRQ_EN,
1138-
"Bad pad config for io mode, force direct_irq_en bit clearing");
1139-
1140-
/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1141-
* are used to indicate high and low level triggering
1142-
*/
1143-
value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1144-
BYT_TRIG_LVL);
1145-
1146-
writel(value, reg);
1147-
1148-
if (type & IRQ_TYPE_EDGE_BOTH)
1149-
irq_set_handler_locked(d, handle_edge_irq);
1150-
else if (type & IRQ_TYPE_LEVEL_MASK)
1151-
irq_set_handler_locked(d, handle_level_irq);
1152-
1153-
raw_spin_unlock_irqrestore(&vg->lock, flags);
1154-
1155-
return 0;
1156-
}
1157-
11581123
static void byt_get_pull_strength(u32 reg, u16 *strength)
11591124
{
11601125
switch (reg & BYT_PULL_STR_MASK) {
@@ -1565,12 +1530,23 @@ static void byt_irq_ack(struct irq_data *d)
15651530
unsigned offset = irqd_to_hwirq(d);
15661531
void __iomem *reg;
15671532

1568-
raw_spin_lock(&vg->lock);
15691533
reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1534+
if (!reg)
1535+
return;
1536+
1537+
raw_spin_lock(&vg->lock);
15701538
writel(BIT(offset % 32), reg);
15711539
raw_spin_unlock(&vg->lock);
15721540
}
15731541

1542+
static void byt_irq_mask(struct irq_data *d)
1543+
{
1544+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1545+
struct byt_gpio *vg = gpiochip_get_data(gc);
1546+
1547+
byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1548+
}
1549+
15741550
static void byt_irq_unmask(struct irq_data *d)
15751551
{
15761552
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -1581,6 +1557,8 @@ static void byt_irq_unmask(struct irq_data *d)
15811557
u32 value;
15821558

15831559
reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1560+
if (!reg)
1561+
return;
15841562

15851563
raw_spin_lock_irqsave(&vg->lock, flags);
15861564
value = readl(reg);
@@ -1606,21 +1584,48 @@ static void byt_irq_unmask(struct irq_data *d)
16061584
raw_spin_unlock_irqrestore(&vg->lock, flags);
16071585
}
16081586

1609-
static void byt_irq_mask(struct irq_data *d)
1587+
static int byt_irq_type(struct irq_data *d, unsigned int type)
16101588
{
1611-
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1612-
struct byt_gpio *vg = gpiochip_get_data(gc);
1589+
struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1590+
u32 offset = irqd_to_hwirq(d);
1591+
u32 value;
1592+
unsigned long flags;
1593+
void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
16131594

1614-
byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1595+
if (!reg || offset >= vg->chip.ngpio)
1596+
return -EINVAL;
1597+
1598+
raw_spin_lock_irqsave(&vg->lock, flags);
1599+
value = readl(reg);
1600+
1601+
WARN(value & BYT_DIRECT_IRQ_EN,
1602+
"Bad pad config for io mode, force direct_irq_en bit clearing");
1603+
1604+
/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1605+
* are used to indicate high and low level triggering
1606+
*/
1607+
value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1608+
BYT_TRIG_LVL);
1609+
1610+
writel(value, reg);
1611+
1612+
if (type & IRQ_TYPE_EDGE_BOTH)
1613+
irq_set_handler_locked(d, handle_edge_irq);
1614+
else if (type & IRQ_TYPE_LEVEL_MASK)
1615+
irq_set_handler_locked(d, handle_level_irq);
1616+
1617+
raw_spin_unlock_irqrestore(&vg->lock, flags);
1618+
1619+
return 0;
16151620
}
16161621

16171622
static struct irq_chip byt_irqchip = {
1618-
.name = "BYT-GPIO",
1619-
.irq_ack = byt_irq_ack,
1620-
.irq_mask = byt_irq_mask,
1621-
.irq_unmask = byt_irq_unmask,
1622-
.irq_set_type = byt_irq_type,
1623-
.flags = IRQCHIP_SKIP_SET_WAKE,
1623+
.name = "BYT-GPIO",
1624+
.irq_ack = byt_irq_ack,
1625+
.irq_mask = byt_irq_mask,
1626+
.irq_unmask = byt_irq_unmask,
1627+
.irq_set_type = byt_irq_type,
1628+
.flags = IRQCHIP_SKIP_SET_WAKE,
16241629
};
16251630

16261631
static void byt_gpio_irq_init_hw(struct byt_gpio *vg)

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