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Alexander DuyckJeff Kirsher
Alexander Duyck
authored and
Jeff Kirsher
committed
i40e/i40evf: Add support for new mechanism of updating adaptive ITR
This patch replaces the existing mechanism for determining the correct value to program for adaptive ITR with yet another new and more complicated approach. The basic idea from a 30K foot view is that this new approach will push the Rx interrupt moderation up so that by default it starts in low latency and is gradually pushed up into a higher latency setup as long as doing so increases the number of packets processed, if the number of packets drops to 4 to 1 per packet we will reset and just base our ITR on the size of the packets being received. For Tx we leave it floating at a high interrupt delay and do not pull it down unless we start processing more than 112 packets per interrupt. If we start exceeding that we will cut our interrupt rates in half until we are back below 112. The side effect of these patches are that we will be processing more packets per interrupt. This is both a good and a bad thing as it means we will not be blocking processing in the case of things like pktgen and XDP, but we will also be consuming a bit more CPU in the cases of things such as network throughput tests using netperf. One delta from this versus the ixgbe version of the changes is that I have made the interrupt moderation a bit more aggressive when we are in bulk mode by moving our "goldilocks zone" up from 48 to 96 to 56 to 112. The main motivation behind moving this is to address the fact that we need to update less frequently, and have more fine grained control due to the separate Tx and Rx ITR times. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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8 files changed

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-257
lines changed

8 files changed

+528
-257
lines changed

‎drivers/net/ethernet/intel/i40e/i40e.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -824,6 +824,7 @@ struct i40e_q_vector {
824824
struct i40e_ring_container rx;
825825
struct i40e_ring_container tx;
826826

827+
u8 itr_countdown; /* when 0 should adjust adaptive ITR */
827828
u8 num_ringpairs; /* total number of ring pairs in vector */
828829

829830
cpumask_t affinity_mask;
@@ -832,8 +833,6 @@ struct i40e_q_vector {
832833
struct rcu_head rcu; /* to avoid race with update stats on free */
833834
char name[I40E_INT_NAME_STR_LEN];
834835
bool arm_wb_state;
835-
#define ITR_COUNTDOWN_START 100
836-
u8 itr_countdown; /* when 0 should adjust ITR */
837836
} ____cacheline_internodealigned_in_smp;
838837

839838
/* lan device */

‎drivers/net/ethernet/intel/i40e/i40e_main.c

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3449,19 +3449,20 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
34493449
for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
34503450
struct i40e_q_vector *q_vector = vsi->q_vectors[i];
34513451

3452-
q_vector->itr_countdown = ITR_COUNTDOWN_START;
3452+
q_vector->rx.next_update = jiffies + 1;
34533453
q_vector->rx.target_itr =
34543454
ITR_TO_REG(vsi->rx_rings[i]->itr_setting);
3455-
q_vector->rx.latency_range = I40E_LOW_LATENCY;
34563455
wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
34573456
q_vector->rx.target_itr);
34583457
q_vector->rx.current_itr = q_vector->rx.target_itr;
3458+
3459+
q_vector->tx.next_update = jiffies + 1;
34593460
q_vector->tx.target_itr =
34603461
ITR_TO_REG(vsi->tx_rings[i]->itr_setting);
3461-
q_vector->tx.latency_range = I40E_LOW_LATENCY;
34623462
wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
34633463
q_vector->tx.target_itr);
34643464
q_vector->tx.current_itr = q_vector->tx.target_itr;
3465+
34653466
wr32(hw, I40E_PFINT_RATEN(vector - 1),
34663467
i40e_intrl_usec_to_reg(vsi->int_rate_limit));
34673468

@@ -3562,13 +3563,12 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
35623563
u32 val;
35633564

35643565
/* set the ITR configuration */
3565-
q_vector->itr_countdown = ITR_COUNTDOWN_START;
3566+
q_vector->rx.next_update = jiffies + 1;
35663567
q_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting);
3567-
q_vector->rx.latency_range = I40E_LOW_LATENCY;
35683568
wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr);
35693569
q_vector->rx.current_itr = q_vector->rx.target_itr;
3570+
q_vector->tx.next_update = jiffies + 1;
35703571
q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting);
3571-
q_vector->tx.latency_range = I40E_LOW_LATENCY;
35723572
wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.target_itr);
35733573
q_vector->tx.current_itr = q_vector->tx.target_itr;
35743574

@@ -10345,9 +10345,6 @@ static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx, int cpu)
1034510345
netif_napi_add(vsi->netdev, &q_vector->napi,
1034610346
i40e_napi_poll, NAPI_POLL_WEIGHT);
1034710347

10348-
q_vector->rx.latency_range = I40E_LOW_LATENCY;
10349-
q_vector->tx.latency_range = I40E_LOW_LATENCY;
10350-
1035110348
/* tie q_vector and vsi together */
1035210349
vsi->q_vectors[v_idx] = q_vector;
1035310350

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