Skip to content

Commit a100ff3

Browse files
Gal PressmanSaeed Mahameed
Gal Pressman
authored and
Saeed Mahameed
committed
net/mlx5e: Fix update of hash function/key via ethtool
Modifying TIR hash should change selected fields bitmask in addition to the function and key. Formerly, Only on ethool mlx5e_set_rxfh "ethtoo -X" we would not set this field resulting in zeroing of its value, which means no packet fields are used for RX RSS hash calculation thus causing all traffic to arrive in RQ[0]. On driver load out of the box we don't have this issue, since the TIR hash is fully created from scratch. Tested: ethtool -X ethX hkey <new key> ethtool -X ethX hfunc <new func> ethtool -X ethX equal <new indirection table> All cases are verified with TCP Multi-Stream traffic over IPv4 & IPv6. Fixes: bdfc028 ("net/mlx5e: Fix ethtool RX hash func configuration change") Signed-off-by: Gal Pressman <galp@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
1 parent 1d3398f commit a100ff3

File tree

3 files changed

+109
-105
lines changed

3 files changed

+109
-105
lines changed

‎drivers/net/ethernet/mellanox/mlx5/core/en.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -791,7 +791,8 @@ void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
791791
int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
792792

793793
int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
794-
void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
794+
void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
795+
enum mlx5e_traffic_types tt);
795796

796797
int mlx5e_open_locked(struct net_device *netdev);
797798
int mlx5e_close_locked(struct net_device *netdev);

‎drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -980,15 +980,18 @@ static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
980980

981981
static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
982982
{
983-
struct mlx5_core_dev *mdev = priv->mdev;
984983
void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
985-
int i;
984+
struct mlx5_core_dev *mdev = priv->mdev;
985+
int ctxlen = MLX5_ST_SZ_BYTES(tirc);
986+
int tt;
986987

987988
MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
988-
mlx5e_build_tir_ctx_hash(tirc, priv);
989989

990-
for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
991-
mlx5_core_modify_tir(mdev, priv->indir_tir[i].tirn, in, inlen);
990+
for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
991+
memset(tirc, 0, ctxlen);
992+
mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt);
993+
mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
994+
}
992995
}
993996

994997
static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,

‎drivers/net/ethernet/mellanox/mlx5/core/en_main.c

Lines changed: 99 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -2022,8 +2022,23 @@ static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
20222022
MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
20232023
}
20242024

2025-
void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
2025+
void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
2026+
enum mlx5e_traffic_types tt)
20262027
{
2028+
void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2029+
2030+
#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2031+
MLX5_HASH_FIELD_SEL_DST_IP)
2032+
2033+
#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2034+
MLX5_HASH_FIELD_SEL_DST_IP |\
2035+
MLX5_HASH_FIELD_SEL_L4_SPORT |\
2036+
MLX5_HASH_FIELD_SEL_L4_DPORT)
2037+
2038+
#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2039+
MLX5_HASH_FIELD_SEL_DST_IP |\
2040+
MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2041+
20272042
MLX5_SET(tirc, tirc, rx_hash_fn,
20282043
mlx5e_rx_hash_fn(priv->params.rss_hfunc));
20292044
if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
@@ -2035,6 +2050,88 @@ void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
20352050
MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
20362051
memcpy(rss_key, priv->params.toeplitz_hash_key, len);
20372052
}
2053+
2054+
switch (tt) {
2055+
case MLX5E_TT_IPV4_TCP:
2056+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2057+
MLX5_L3_PROT_TYPE_IPV4);
2058+
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2059+
MLX5_L4_PROT_TYPE_TCP);
2060+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2061+
MLX5_HASH_IP_L4PORTS);
2062+
break;
2063+
2064+
case MLX5E_TT_IPV6_TCP:
2065+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2066+
MLX5_L3_PROT_TYPE_IPV6);
2067+
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2068+
MLX5_L4_PROT_TYPE_TCP);
2069+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2070+
MLX5_HASH_IP_L4PORTS);
2071+
break;
2072+
2073+
case MLX5E_TT_IPV4_UDP:
2074+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2075+
MLX5_L3_PROT_TYPE_IPV4);
2076+
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2077+
MLX5_L4_PROT_TYPE_UDP);
2078+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2079+
MLX5_HASH_IP_L4PORTS);
2080+
break;
2081+
2082+
case MLX5E_TT_IPV6_UDP:
2083+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2084+
MLX5_L3_PROT_TYPE_IPV6);
2085+
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2086+
MLX5_L4_PROT_TYPE_UDP);
2087+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2088+
MLX5_HASH_IP_L4PORTS);
2089+
break;
2090+
2091+
case MLX5E_TT_IPV4_IPSEC_AH:
2092+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2093+
MLX5_L3_PROT_TYPE_IPV4);
2094+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095+
MLX5_HASH_IP_IPSEC_SPI);
2096+
break;
2097+
2098+
case MLX5E_TT_IPV6_IPSEC_AH:
2099+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2100+
MLX5_L3_PROT_TYPE_IPV6);
2101+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2102+
MLX5_HASH_IP_IPSEC_SPI);
2103+
break;
2104+
2105+
case MLX5E_TT_IPV4_IPSEC_ESP:
2106+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2107+
MLX5_L3_PROT_TYPE_IPV4);
2108+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2109+
MLX5_HASH_IP_IPSEC_SPI);
2110+
break;
2111+
2112+
case MLX5E_TT_IPV6_IPSEC_ESP:
2113+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2114+
MLX5_L3_PROT_TYPE_IPV6);
2115+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2116+
MLX5_HASH_IP_IPSEC_SPI);
2117+
break;
2118+
2119+
case MLX5E_TT_IPV4:
2120+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2121+
MLX5_L3_PROT_TYPE_IPV4);
2122+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2123+
MLX5_HASH_IP);
2124+
break;
2125+
2126+
case MLX5E_TT_IPV6:
2127+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2128+
MLX5_L3_PROT_TYPE_IPV6);
2129+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2130+
MLX5_HASH_IP);
2131+
break;
2132+
default:
2133+
WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2134+
}
20382135
}
20392136

20402137
static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
@@ -2404,110 +2501,13 @@ void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
24042501
static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
24052502
enum mlx5e_traffic_types tt)
24062503
{
2407-
void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2408-
24092504
MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
24102505

2411-
#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2412-
MLX5_HASH_FIELD_SEL_DST_IP)
2413-
2414-
#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2415-
MLX5_HASH_FIELD_SEL_DST_IP |\
2416-
MLX5_HASH_FIELD_SEL_L4_SPORT |\
2417-
MLX5_HASH_FIELD_SEL_L4_DPORT)
2418-
2419-
#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2420-
MLX5_HASH_FIELD_SEL_DST_IP |\
2421-
MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2422-
24232506
mlx5e_build_tir_ctx_lro(tirc, priv);
24242507

24252508
MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
24262509
MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2427-
mlx5e_build_tir_ctx_hash(tirc, priv);
2428-
2429-
switch (tt) {
2430-
case MLX5E_TT_IPV4_TCP:
2431-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2432-
MLX5_L3_PROT_TYPE_IPV4);
2433-
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2434-
MLX5_L4_PROT_TYPE_TCP);
2435-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436-
MLX5_HASH_IP_L4PORTS);
2437-
break;
2438-
2439-
case MLX5E_TT_IPV6_TCP:
2440-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441-
MLX5_L3_PROT_TYPE_IPV6);
2442-
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2443-
MLX5_L4_PROT_TYPE_TCP);
2444-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2445-
MLX5_HASH_IP_L4PORTS);
2446-
break;
2447-
2448-
case MLX5E_TT_IPV4_UDP:
2449-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2450-
MLX5_L3_PROT_TYPE_IPV4);
2451-
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2452-
MLX5_L4_PROT_TYPE_UDP);
2453-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2454-
MLX5_HASH_IP_L4PORTS);
2455-
break;
2456-
2457-
case MLX5E_TT_IPV6_UDP:
2458-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2459-
MLX5_L3_PROT_TYPE_IPV6);
2460-
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2461-
MLX5_L4_PROT_TYPE_UDP);
2462-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2463-
MLX5_HASH_IP_L4PORTS);
2464-
break;
2465-
2466-
case MLX5E_TT_IPV4_IPSEC_AH:
2467-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2468-
MLX5_L3_PROT_TYPE_IPV4);
2469-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2470-
MLX5_HASH_IP_IPSEC_SPI);
2471-
break;
2472-
2473-
case MLX5E_TT_IPV6_IPSEC_AH:
2474-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2475-
MLX5_L3_PROT_TYPE_IPV6);
2476-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2477-
MLX5_HASH_IP_IPSEC_SPI);
2478-
break;
2479-
2480-
case MLX5E_TT_IPV4_IPSEC_ESP:
2481-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2482-
MLX5_L3_PROT_TYPE_IPV4);
2483-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2484-
MLX5_HASH_IP_IPSEC_SPI);
2485-
break;
2486-
2487-
case MLX5E_TT_IPV6_IPSEC_ESP:
2488-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2489-
MLX5_L3_PROT_TYPE_IPV6);
2490-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2491-
MLX5_HASH_IP_IPSEC_SPI);
2492-
break;
2493-
2494-
case MLX5E_TT_IPV4:
2495-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2496-
MLX5_L3_PROT_TYPE_IPV4);
2497-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2498-
MLX5_HASH_IP);
2499-
break;
2500-
2501-
case MLX5E_TT_IPV6:
2502-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2503-
MLX5_L3_PROT_TYPE_IPV6);
2504-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2505-
MLX5_HASH_IP);
2506-
break;
2507-
default:
2508-
WARN_ONCE(true,
2509-
"mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2510-
}
2510+
mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt);
25112511
}
25122512

25132513
static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,

0 commit comments

Comments
 (0)