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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS: - a number of fixes that didn't make the 3.19 release. - a number of cleanups. - preliminary support for Cavium's Octeon 3 SOCs which feature up to 48 MIPS64 R3 cores with FPU and hardware virtualization. - support for MIPS R6 processors. Revision 6 of the MIPS architecture is a major revision of the MIPS architecture which does away with many of original sins of the architecture such as branch delay slots. This and other changes in R6 require major changes throughout the entire MIPS core architecture code and make up for the lion share of this pull request. - finally some preparatory work for eXtendend Physical Address support, which allows support of up to 40 bit of physical address space on 32 bit processors" [ Ahh, MIPS can't leave the PAE brain damage alone. It's like every CPU architect has to make that mistake, but pee in the snow by changing the TLA. But whether it's called PAE, LPAE or XPA, it's horrid crud - Linus ] * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (114 commits) MIPS: sead3: Corrected get_c0_perfcount_int MIPS: mm: Remove dead macro definitions MIPS: OCTEON: irq: add CIB and other fixes MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs. MIPS: OCTEON: More OCTEONIII support MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits. MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup. MIPS: OCTEON: Update octeon-model.h code for new SoCs. MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h MIPS: OCTEON: Implement the core-16057 workaround MIPS: OCTEON: Delete unused COP2 saving code MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register MIPS: OCTEON: Save and restore CP2 SHA3 state MIPS: OCTEON: Fix FP context save. MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs MIPS: boot: Provide more uImage options MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h MIPS: ip22-gio: Remove legacy suspend/resume support mips: pci: Add ifdef around pci_proc_domain ...
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‎Documentation/devicetree/bindings/mips/cavium/cib.txt

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
* Cavium Interrupt Bus widget
2+
3+
Properties:
4+
- compatible: "cavium,octeon-7130-cib"
5+
6+
Compatibility with cn70XX SoCs.
7+
8+
- interrupt-controller: This is an interrupt controller.
9+
10+
- reg: Two elements consisting of the addresses of the RAW and EN
11+
registers of the CIB block
12+
13+
- cavium,max-bits: The index (zero based) of the highest numbered bit
14+
in the CIB block.
15+
16+
- interrupt-parent: Always the CIU on the SoC.
17+
18+
- interrupts: The CIU line to which the CIB block is connected.
19+
20+
- #interrupt-cells: Must be <2>. The first cell is the bit within the
21+
CIB. The second cell specifies the triggering semantics of the
22+
line.
23+
24+
Example:
25+
26+
interrupt-controller@107000000e000 {
27+
compatible = "cavium,octeon-7130-cib";
28+
reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
29+
<0x10700 0x0000e100 0x0 0x8>; /* EN */
30+
cavium,max-bits = <23>;
31+
32+
interrupt-controller;
33+
interrupt-parent = <&ciu>;
34+
interrupts = <1 24>;
35+
/* Interrupts are specified by two parts:
36+
* 1) Bit number in the CIB* registers
37+
* 2) Triggering (1 - edge rising
38+
* 2 - edge falling
39+
* 4 - level active high
40+
* 8 - level active low)
41+
*/
42+
#interrupt-cells = <2>;
43+
};

‎arch/mips/Kconfig

Lines changed: 69 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ config MIPS
5454
select CPU_PM if CPU_IDLE
5555
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
5656
select ARCH_BINFMT_ELF_STATE
57+
select SYSCTL_EXCEPTION_TRACE
5758

5859
menu "Machine selection"
5960

@@ -376,8 +377,10 @@ config MIPS_MALTA
376377
select SYS_HAS_CPU_MIPS32_R1
377378
select SYS_HAS_CPU_MIPS32_R2
378379
select SYS_HAS_CPU_MIPS32_R3_5
380+
select SYS_HAS_CPU_MIPS32_R6
379381
select SYS_HAS_CPU_MIPS64_R1
380382
select SYS_HAS_CPU_MIPS64_R2
383+
select SYS_HAS_CPU_MIPS64_R6
381384
select SYS_HAS_CPU_NEVADA
382385
select SYS_HAS_CPU_RM7000
383386
select SYS_SUPPORTS_32BIT_KERNEL
@@ -1033,6 +1036,9 @@ config MIPS_MACHINE
10331036
config NO_IOPORT_MAP
10341037
def_bool n
10351038

1039+
config GENERIC_CSUM
1040+
bool
1041+
10361042
config GENERIC_ISA_DMA
10371043
bool
10381044
select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
@@ -1146,6 +1152,9 @@ config SOC_PNX8335
11461152
bool
11471153
select SOC_PNX833X
11481154

1155+
config MIPS_SPRAM
1156+
bool
1157+
11491158
config SWAP_IO_SPACE
11501159
bool
11511160

@@ -1304,6 +1313,22 @@ config CPU_MIPS32_R2
13041313
specific type of processor in your system, choose those that one
13051314
otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
13061315

1316+
config CPU_MIPS32_R6
1317+
bool "MIPS32 Release 6 (EXPERIMENTAL)"
1318+
depends on SYS_HAS_CPU_MIPS32_R6
1319+
select CPU_HAS_PREFETCH
1320+
select CPU_SUPPORTS_32BIT_KERNEL
1321+
select CPU_SUPPORTS_HIGHMEM
1322+
select CPU_SUPPORTS_MSA
1323+
select GENERIC_CSUM
1324+
select HAVE_KVM
1325+
select MIPS_O32_FP64_SUPPORT
1326+
help
1327+
Choose this option to build a kernel for release 6 or later of the
1328+
MIPS32 architecture. New MIPS processors, starting with the Warrior
1329+
family, are based on a MIPS32r6 processor. If you own an older
1330+
processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1331+
13071332
config CPU_MIPS64_R1
13081333
bool "MIPS64 Release 1"
13091334
depends on SYS_HAS_CPU_MIPS64_R1
@@ -1339,6 +1364,21 @@ config CPU_MIPS64_R2
13391364
specific type of processor in your system, choose those that one
13401365
otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
13411366

1367+
config CPU_MIPS64_R6
1368+
bool "MIPS64 Release 6 (EXPERIMENTAL)"
1369+
depends on SYS_HAS_CPU_MIPS64_R6
1370+
select CPU_HAS_PREFETCH
1371+
select CPU_SUPPORTS_32BIT_KERNEL
1372+
select CPU_SUPPORTS_64BIT_KERNEL
1373+
select CPU_SUPPORTS_HIGHMEM
1374+
select CPU_SUPPORTS_MSA
1375+
select GENERIC_CSUM
1376+
help
1377+
Choose this option to build a kernel for release 6 or later of the
1378+
MIPS64 architecture. New MIPS processors, starting with the Warrior
1379+
family, are based on a MIPS64r6 processor. If you own an older
1380+
processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1381+
13421382
config CPU_R3000
13431383
bool "R3000"
13441384
depends on SYS_HAS_CPU_R3000
@@ -1539,7 +1579,7 @@ endchoice
15391579
config CPU_MIPS32_3_5_FEATURES
15401580
bool "MIPS32 Release 3.5 Features"
15411581
depends on SYS_HAS_CPU_MIPS32_R3_5
1542-
depends on CPU_MIPS32_R2
1582+
depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
15431583
help
15441584
Choose this option to build a kernel for release 2 or later of the
15451585
MIPS32 architecture including features from the 3.5 release such as
@@ -1659,12 +1699,18 @@ config SYS_HAS_CPU_MIPS32_R2
16591699
config SYS_HAS_CPU_MIPS32_R3_5
16601700
bool
16611701

1702+
config SYS_HAS_CPU_MIPS32_R6
1703+
bool
1704+
16621705
config SYS_HAS_CPU_MIPS64_R1
16631706
bool
16641707

16651708
config SYS_HAS_CPU_MIPS64_R2
16661709
bool
16671710

1711+
config SYS_HAS_CPU_MIPS64_R6
1712+
bool
1713+
16681714
config SYS_HAS_CPU_R3000
16691715
bool
16701716

@@ -1764,11 +1810,11 @@ endmenu
17641810
#
17651811
config CPU_MIPS32
17661812
bool
1767-
default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
1813+
default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
17681814

17691815
config CPU_MIPS64
17701816
bool
1771-
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
1817+
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
17721818

17731819
#
17741820
# These two indicate the revision of the architecture, either Release 1 or Release 2
@@ -1780,6 +1826,12 @@ config CPU_MIPSR1
17801826
config CPU_MIPSR2
17811827
bool
17821828
default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1829+
select MIPS_SPRAM
1830+
1831+
config CPU_MIPSR6
1832+
bool
1833+
default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
1834+
select MIPS_SPRAM
17831835

17841836
config EVA
17851837
bool
@@ -2013,6 +2065,19 @@ config MIPS_MT_FPAFF
20132065
default y
20142066
depends on MIPS_MT_SMP
20152067

2068+
config MIPSR2_TO_R6_EMULATOR
2069+
bool "MIPS R2-to-R6 emulator"
2070+
depends on CPU_MIPSR6 && !SMP
2071+
default y
2072+
help
2073+
Choose this option if you want to run non-R6 MIPS userland code.
2074+
Even if you say 'Y' here, the emulator will still be disabled by
2075+
default. You can enable it using the 'mipsr2emul' kernel option.
2076+
The only reason this is a build-time option is to save ~14K from the
2077+
final kernel image.
2078+
comment "MIPS R2-to-R6 emulator is only available for UP kernels"
2079+
depends on SMP && CPU_MIPSR6
2080+
20162081
config MIPS_VPE_LOADER
20172082
bool "VPE loader support."
20182083
depends on SYS_SUPPORTS_MULTITHREADING && MODULES
@@ -2148,7 +2213,7 @@ config CPU_HAS_SMARTMIPS
21482213
here.
21492214

21502215
config CPU_MICROMIPS
2151-
depends on 32BIT && SYS_SUPPORTS_MICROMIPS
2216+
depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
21522217
bool "microMIPS"
21532218
help
21542219
When this option is enabled the kernel will be built using the

‎arch/mips/Kconfig.debug

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -122,17 +122,4 @@ config SPINLOCK_TEST
122122
help
123123
Add several files to the debugfs to test spinlock speed.
124124

125-
config FP32XX_HYBRID_FPRS
126-
bool "Run FP32 & FPXX code with hybrid FPRs"
127-
depends on MIPS_O32_FP64_SUPPORT
128-
help
129-
The hybrid FPR scheme is normally used only when a program needs to
130-
execute a mix of FP32 & FP64A code, since the trapping & emulation
131-
that it entails is expensive. When enabled, this option will lead
132-
to the kernel running programs which use the FP32 & FPXX FP ABIs
133-
using the hybrid FPR scheme, which can be useful for debugging
134-
purposes.
135-
136-
If unsure, say N.
137-
138125
endmenu

‎arch/mips/Makefile

Lines changed: 37 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -122,26 +122,8 @@ predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__
122122
cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))
123123
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
124124

125-
# For smartmips configurations, there are hundreds of warnings due to ISA overrides
126-
# in assembly and header files. smartmips is only supported for MIPS32r1 onwards
127-
# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
128-
# similar directives in the kernel will spam the build logs with the following warnings:
129-
# Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
130-
# or
131-
# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
132-
# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
133-
# been fixed properly.
134-
cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips) -Wa,--no-warn
135-
cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
136-
137125
cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
138126
-fno-omit-frame-pointer
139-
140-
ifeq ($(CONFIG_CPU_HAS_MSA),y)
141-
toolchain-msa := $(call cc-option-yn,-mhard-float -mfp64 -Wa$(comma)-mmsa)
142-
cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
143-
endif
144-
145127
#
146128
# CPU-dependent compiler/assembler options for optimization.
147129
#
@@ -156,10 +138,12 @@ cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS
156138
-Wa,-mips32 -Wa,--trap
157139
cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
158140
-Wa,-mips32r2 -Wa,--trap
141+
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap
159142
cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
160143
-Wa,-mips64 -Wa,--trap
161144
cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
162145
-Wa,-mips64r2 -Wa,--trap
146+
cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap
163147
cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap
164148
cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \
165149
-Wa,--trap
@@ -182,6 +166,16 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
182166
endif
183167
cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
184168
cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap
169+
#
170+
# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
171+
# as MIPS64 R1; older versions as just R1. This leaves the possibility open
172+
# that GCC might generate R2 code for -march=loongson3a which then is rejected
173+
# by GAS. The cc-option can't probe for this behaviour so -march=loongson3a
174+
# can't easily be used safely within the kbuild framework.
175+
#
176+
cflags-$(CONFIG_CPU_LOONGSON3) += \
177+
$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
178+
-Wa,-mips64r2 -Wa,--trap
185179

186180
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
187181
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
@@ -194,6 +188,23 @@ KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds
194188
endif
195189
endif
196190

191+
# For smartmips configurations, there are hundreds of warnings due to ISA overrides
192+
# in assembly and header files. smartmips is only supported for MIPS32r1 onwards
193+
# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
194+
# similar directives in the kernel will spam the build logs with the following warnings:
195+
# Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
196+
# or
197+
# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
198+
# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
199+
# been fixed properly.
200+
mips-cflags := "$(cflags-y)"
201+
cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn
202+
cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,$(mips-cflags),-mmicromips)
203+
ifeq ($(CONFIG_CPU_HAS_MSA),y)
204+
toolchain-msa := $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa)
205+
cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
206+
endif
207+
197208
#
198209
# Firmware support
199210
#
@@ -287,7 +298,11 @@ boot-y += vmlinux.ecoff
287298
boot-y += vmlinux.srec
288299
ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)
289300
boot-y += uImage
301+
boot-y += uImage.bin
302+
boot-y += uImage.bz2
290303
boot-y += uImage.gz
304+
boot-y += uImage.lzma
305+
boot-y += uImage.lzo
291306
endif
292307

293308
# compressed boot image targets (arch/mips/boot/compressed/)
@@ -386,7 +401,11 @@ define archhelp
386401
echo ' vmlinuz.bin - Raw binary zboot image'
387402
echo ' vmlinuz.srec - SREC zboot image'
388403
echo ' uImage - U-Boot image'
404+
echo ' uImage.bin - U-Boot image (uncompressed)'
405+
echo ' uImage.bz2 - U-Boot image (bz2)'
389406
echo ' uImage.gz - U-Boot image (gzip)'
407+
echo ' uImage.lzma - U-Boot image (lzma)'
408+
echo ' uImage.lzo - U-Boot image (lzo)'
390409
echo ' dtbs - Device-tree blobs for enabled boards'
391410
echo
392411
echo ' These will be default as appropriate for a configured platform.'

‎arch/mips/alchemy/common/clock.c

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -127,12 +127,20 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
127127
t = 396000000;
128128
else {
129129
t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
130+
if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
131+
t &= 0x3f;
130132
t *= parent_rate;
131133
}
132134

133135
return t;
134136
}
135137

138+
void __init alchemy_set_lpj(void)
139+
{
140+
preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE);
141+
preset_lpj /= 2 * HZ;
142+
}
143+
136144
static struct clk_ops alchemy_clkops_cpu = {
137145
.recalc_rate = alchemy_clk_cpu_recalc,
138146
};
@@ -315,17 +323,26 @@ static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
315323

316324
/* lrclk: external synchronous static bus clock ***********************/
317325

318-
static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
326+
static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
319327
{
320-
/* MEM_STCFG0[15:13] = divisor.
328+
/* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
329+
* otherwise lrclk=pclk/4.
330+
* All other variants: MEM_STCFG0[15:13] = divisor.
321331
* L/RCLK = periph_clk / (divisor + 1)
322332
* On Au1000, Au1500, Au1100 it's called LCLK,
323333
* on later models it's called RCLK, but it's the same thing.
324334
*/
325335
struct clk *c;
326-
unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
336+
unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
327337

328-
v = (v & 7) + 1;
338+
switch (t) {
339+
case ALCHEMY_CPU_AU1000:
340+
case ALCHEMY_CPU_AU1500:
341+
v = 4 + ((v >> 11) & 1);
342+
break;
343+
default: /* all other models */
344+
v = ((v >> 13) & 7) + 1;
345+
}
329346
c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
330347
pn, 0, 1, v);
331348
if (!IS_ERR(c))
@@ -1066,7 +1083,7 @@ static int __init alchemy_clk_init(void)
10661083
ERRCK(c)
10671084

10681085
/* L/RCLK: external static bus clock for synchronous mode */
1069-
c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
1086+
c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
10701087
ERRCK(c)
10711088

10721089
/* Frequency dividers 0-5 */

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