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MIPS: Move r4k FP code from r4k_switch.S to r4k_fpu.S
Move _save_fp(), _restore_fp(), _save_msa(), _restore_msa(), _init_msa_upper() & _init_fpu() out of r4k_switch.S & into r4k_fpu.S. This allows us to clean up the way in which Octeon includes the default r4k implementations of these FP functions despite replacing resume(), and makes CONFIG_R4K_FPU more straightforwardly represent all configurations that have an R4K-style FPU, including Octeon. Besides cleaning up this will be useful for later patches which disable FP support. [ralf@linux-mips.org: Fixed build issues reported by Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16237/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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5 files changed

+212
-213
lines changed

5 files changed

+212
-213
lines changed

‎arch/mips/Kconfig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2241,7 +2241,7 @@ config CPU_GENERIC_DUMP_TLB
22412241

22422242
config CPU_R4K_FPU
22432243
bool
2244-
default y if !(CPU_R3000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
2244+
default y if !(CPU_R3000 || CPU_TX39XX)
22452245

22462246
config CPU_R4K_CACHE_TLB
22472247
bool

‎arch/mips/kernel/Makefile

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,15 @@ obj-$(CONFIG_MODULES) += module.o
3535
obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
3636
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
3737

38-
obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
39-
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
40-
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
41-
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o
38+
sw-y := r4k_switch.o
39+
sw-$(CONFIG_CPU_R3000) := r2300_switch.o
40+
sw-$(CONFIG_CPU_TX39XX) := r2300_switch.o
41+
sw-$(CONFIG_CPU_CAVIUM_OCTEON) := octeon_switch.o
42+
obj-y += $(sw-y)
43+
44+
obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o
45+
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o
46+
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o
4247

4348
obj-$(CONFIG_SMP) += smp.o
4449
obj-$(CONFIG_SMP_UP) += smp-up.o

‎arch/mips/kernel/octeon_switch.S

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,13 @@
1010
* Copyright (C) 2000 MIPS Technologies, Inc.
1111
* written by Carsten Langgaard, carstenl@mips.com
1212
*/
13+
#include <asm/asm.h>
14+
#include <asm/export.h>
15+
#include <asm/asm-offsets.h>
16+
#include <asm/mipsregs.h>
17+
#include <asm/regdef.h>
18+
#include <asm/stackframe.h>
1319

14-
#define USE_ALTERNATE_RESUME_IMPL 1
15-
.set push
16-
.set arch=mips64r2
17-
#include "r4k_switch.S"
18-
.set pop
1920
/*
2021
* task_struct *resume(task_struct *prev, task_struct *next,
2122
* struct thread_info *next_ti)

‎arch/mips/kernel/r4k_fpu.S

Lines changed: 196 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <asm/asm.h>
1616
#include <asm/asmmacro.h>
1717
#include <asm/errno.h>
18+
#include <asm/export.h>
1819
#include <asm/fpregdef.h>
1920
#include <asm/mipsregs.h>
2021
#include <asm/asm-offsets.h>
@@ -34,6 +35,201 @@
3435
.previous
3536
.endm
3637

38+
/*
39+
* Save a thread's fp context.
40+
*/
41+
LEAF(_save_fp)
42+
EXPORT_SYMBOL(_save_fp)
43+
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
44+
defined(CONFIG_CPU_MIPS32_R6)
45+
mfc0 t0, CP0_STATUS
46+
#endif
47+
fpu_save_double a0 t0 t1 # clobbers t1
48+
jr ra
49+
END(_save_fp)
50+
51+
/*
52+
* Restore a thread's fp context.
53+
*/
54+
LEAF(_restore_fp)
55+
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
56+
defined(CONFIG_CPU_MIPS32_R6)
57+
mfc0 t0, CP0_STATUS
58+
#endif
59+
fpu_restore_double a0 t0 t1 # clobbers t1
60+
jr ra
61+
END(_restore_fp)
62+
63+
#ifdef CONFIG_CPU_HAS_MSA
64+
65+
/*
66+
* Save a thread's MSA vector context.
67+
*/
68+
LEAF(_save_msa)
69+
EXPORT_SYMBOL(_save_msa)
70+
msa_save_all a0
71+
jr ra
72+
END(_save_msa)
73+
74+
/*
75+
* Restore a thread's MSA vector context.
76+
*/
77+
LEAF(_restore_msa)
78+
msa_restore_all a0
79+
jr ra
80+
END(_restore_msa)
81+
82+
LEAF(_init_msa_upper)
83+
msa_init_all_upper
84+
jr ra
85+
END(_init_msa_upper)
86+
87+
#endif
88+
89+
/*
90+
* Load the FPU with signalling NANS. This bit pattern we're using has
91+
* the property that no matter whether considered as single or as double
92+
* precision represents signaling NANS.
93+
*
94+
* The value to initialize fcr31 to comes in $a0.
95+
*/
96+
97+
.set push
98+
SET_HARDFLOAT
99+
100+
LEAF(_init_fpu)
101+
mfc0 t0, CP0_STATUS
102+
li t1, ST0_CU1
103+
or t0, t1
104+
mtc0 t0, CP0_STATUS
105+
enable_fpu_hazard
106+
107+
ctc1 a0, fcr31
108+
109+
li t1, -1 # SNaN
110+
111+
#ifdef CONFIG_64BIT
112+
sll t0, t0, 5
113+
bgez t0, 1f # 16 / 32 register mode?
114+
115+
dmtc1 t1, $f1
116+
dmtc1 t1, $f3
117+
dmtc1 t1, $f5
118+
dmtc1 t1, $f7
119+
dmtc1 t1, $f9
120+
dmtc1 t1, $f11
121+
dmtc1 t1, $f13
122+
dmtc1 t1, $f15
123+
dmtc1 t1, $f17
124+
dmtc1 t1, $f19
125+
dmtc1 t1, $f21
126+
dmtc1 t1, $f23
127+
dmtc1 t1, $f25
128+
dmtc1 t1, $f27
129+
dmtc1 t1, $f29
130+
dmtc1 t1, $f31
131+
1:
132+
#endif
133+
134+
#ifdef CONFIG_CPU_MIPS32
135+
mtc1 t1, $f0
136+
mtc1 t1, $f1
137+
mtc1 t1, $f2
138+
mtc1 t1, $f3
139+
mtc1 t1, $f4
140+
mtc1 t1, $f5
141+
mtc1 t1, $f6
142+
mtc1 t1, $f7
143+
mtc1 t1, $f8
144+
mtc1 t1, $f9
145+
mtc1 t1, $f10
146+
mtc1 t1, $f11
147+
mtc1 t1, $f12
148+
mtc1 t1, $f13
149+
mtc1 t1, $f14
150+
mtc1 t1, $f15
151+
mtc1 t1, $f16
152+
mtc1 t1, $f17
153+
mtc1 t1, $f18
154+
mtc1 t1, $f19
155+
mtc1 t1, $f20
156+
mtc1 t1, $f21
157+
mtc1 t1, $f22
158+
mtc1 t1, $f23
159+
mtc1 t1, $f24
160+
mtc1 t1, $f25
161+
mtc1 t1, $f26
162+
mtc1 t1, $f27
163+
mtc1 t1, $f28
164+
mtc1 t1, $f29
165+
mtc1 t1, $f30
166+
mtc1 t1, $f31
167+
168+
#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)
169+
.set push
170+
.set MIPS_ISA_LEVEL_RAW
171+
.set fp=64
172+
sll t0, t0, 5 # is Status.FR set?
173+
bgez t0, 1f # no: skip setting upper 32b
174+
175+
mthc1 t1, $f0
176+
mthc1 t1, $f1
177+
mthc1 t1, $f2
178+
mthc1 t1, $f3
179+
mthc1 t1, $f4
180+
mthc1 t1, $f5
181+
mthc1 t1, $f6
182+
mthc1 t1, $f7
183+
mthc1 t1, $f8
184+
mthc1 t1, $f9
185+
mthc1 t1, $f10
186+
mthc1 t1, $f11
187+
mthc1 t1, $f12
188+
mthc1 t1, $f13
189+
mthc1 t1, $f14
190+
mthc1 t1, $f15
191+
mthc1 t1, $f16
192+
mthc1 t1, $f17
193+
mthc1 t1, $f18
194+
mthc1 t1, $f19
195+
mthc1 t1, $f20
196+
mthc1 t1, $f21
197+
mthc1 t1, $f22
198+
mthc1 t1, $f23
199+
mthc1 t1, $f24
200+
mthc1 t1, $f25
201+
mthc1 t1, $f26
202+
mthc1 t1, $f27
203+
mthc1 t1, $f28
204+
mthc1 t1, $f29
205+
mthc1 t1, $f30
206+
mthc1 t1, $f31
207+
1: .set pop
208+
#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */
209+
#else
210+
.set MIPS_ISA_ARCH_LEVEL_RAW
211+
dmtc1 t1, $f0
212+
dmtc1 t1, $f2
213+
dmtc1 t1, $f4
214+
dmtc1 t1, $f6
215+
dmtc1 t1, $f8
216+
dmtc1 t1, $f10
217+
dmtc1 t1, $f12
218+
dmtc1 t1, $f14
219+
dmtc1 t1, $f16
220+
dmtc1 t1, $f18
221+
dmtc1 t1, $f20
222+
dmtc1 t1, $f22
223+
dmtc1 t1, $f24
224+
dmtc1 t1, $f26
225+
dmtc1 t1, $f28
226+
dmtc1 t1, $f30
227+
#endif
228+
jr ra
229+
END(_init_fpu)
230+
231+
.set pop /* SET_HARDFLOAT */
232+
37233
.set noreorder
38234

39235
/**

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