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Sunil Gouthamdavem330
Sunil Goutham
authored and
davem330
committed
net: thunderx: Moved HW capability info from macros to structure
Current driver has most of the HW maximums info like no of channels, traffic limiters, RSS indices e.t.c in the form of macros. These have been moved into a 'hw_info' structure so that support for VNIC on newer chips with different set of HW maximums can be added. Signed-off-by: Sunil Goutham <sgoutham@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent 2ce66f9 commit a5c3d49

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+85
-52
lines changed

2 files changed

+85
-52
lines changed

‎drivers/net/ethernet/cavium/thunder/nic.h

Lines changed: 6 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,9 @@
2020
#define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034
2121
#define PCI_DEVICE_ID_THUNDER_BGX 0xA026
2222

23+
/* Subsystem device IDs */
24+
#define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E
25+
2326
/* PCI BAR nos */
2427
#define PCI_CFG_REG_BAR_NUM 0
2528
#define PCI_MSIX_REG_BAR_NUM 4
@@ -41,40 +44,8 @@
4144
/* Max pkinds */
4245
#define NIC_MAX_PKIND 16
4346

44-
/* Rx Channels */
45-
/* Receive channel configuration in TNS bypass mode
46-
* Below is configuration in TNS bypass mode
47-
* BGX0-LMAC0-CHAN0 - VNIC CHAN0
48-
* BGX0-LMAC1-CHAN0 - VNIC CHAN16
49-
* ...
50-
* BGX1-LMAC0-CHAN0 - VNIC CHAN128
51-
* ...
52-
* BGX1-LMAC3-CHAN0 - VNIC CHAN174
53-
*/
54-
#define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */
55-
#define NIC_CHANS_PER_INF 128
56-
#define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF)
57-
#define NIC_CPI_COUNT 2048 /* No of channel parse indices */
58-
59-
/* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */
60-
#define NIC_MAX_BGX MAX_BGX_PER_CN88XX
61-
#define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX)
62-
#define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */
63-
#define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX)
64-
65-
/* Tx scheduling */
66-
#define NIC_MAX_TL4 1024
67-
#define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */
68-
#define NIC_MAX_TL3 256
69-
#define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */
70-
#define NIC_MAX_TL2 64
71-
#define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */
72-
#define NIC_MAX_TL1 2
73-
74-
/* TNS bypass mode */
75-
#define NIC_TL2_PER_BGX 32
76-
#define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX)
77-
#define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF)
47+
/* Max when CPI_ALG is IP diffserv */
48+
#define NIC_MAX_CPI_PER_LMAC 64
7849

7950
/* NIC VF Interrupts */
8051
#define NICVF_INTR_CQ 0
@@ -148,7 +119,6 @@ struct nicvf_cq_poll {
148119
struct napi_struct napi;
149120
};
150121

151-
#define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */
152122
#define NIC_MAX_RSS_HASH_BITS 8
153123
#define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
154124
#define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
@@ -273,6 +243,7 @@ struct nicvf {
273243
struct net_device *netdev;
274244
struct pci_dev *pdev;
275245
void __iomem *reg_base;
246+
#define MAX_QUEUES_PER_QSET 8
276247
struct queue_set *qs;
277248
struct nicvf_cq_poll *napi[8];
278249
u8 vf_id;

‎drivers/net/ethernet/cavium/thunder/nic_main.c

Lines changed: 79 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,23 @@
2020
#define DRV_NAME "thunder-nic"
2121
#define DRV_VERSION "1.0"
2222

23+
struct hw_info {
24+
u8 bgx_cnt;
25+
u8 chans_per_lmac;
26+
u8 chans_per_bgx; /* Rx/Tx chans */
27+
u16 cpi_cnt;
28+
u16 rssi_cnt;
29+
u16 rss_ind_tbl_size;
30+
u16 tl4_cnt;
31+
u16 tl3_cnt;
32+
u8 tl2_cnt;
33+
u8 tl1_cnt;
34+
bool tl1_per_bgx; /* TL1 per BGX or per LMAC */
35+
};
36+
2337
struct nicpf {
2438
struct pci_dev *pdev;
39+
struct hw_info *hw;
2540
u8 node;
2641
unsigned int flags;
2742
u8 num_vf_en; /* No of VF enabled */
@@ -44,7 +59,6 @@ struct nicpf {
4459
u32 speed[MAX_LMAC];
4560
u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
4661
u16 rssi_base[MAX_NUM_VFS_SUPPORTED];
47-
u16 rss_ind_tbl_size;
4862
bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
4963

5064
/* MSI-X */
@@ -275,7 +289,7 @@ static void nic_set_lmac_vf_mapping(struct nicpf *nic)
275289

276290
nic->num_vf_en = 0;
277291

278-
for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) {
292+
for (bgx = 0; bgx < nic->hw->bgx_cnt; bgx++) {
279293
if (!(bgx_map & (1 << bgx)))
280294
continue;
281295
lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
@@ -298,6 +312,30 @@ static void nic_set_lmac_vf_mapping(struct nicpf *nic)
298312
}
299313
}
300314

315+
static void nic_get_hw_info(struct nicpf *nic)
316+
{
317+
u16 sdevid;
318+
struct hw_info *hw = nic->hw;
319+
320+
pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
321+
322+
switch (sdevid) {
323+
case PCI_SUBSYS_DEVID_88XX_NIC_PF:
324+
hw->bgx_cnt = MAX_BGX_PER_CN88XX;
325+
hw->chans_per_lmac = 16;
326+
hw->chans_per_bgx = 128;
327+
hw->cpi_cnt = 2048;
328+
hw->rssi_cnt = 4096;
329+
hw->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
330+
hw->tl3_cnt = 256;
331+
hw->tl2_cnt = 64;
332+
hw->tl1_cnt = 2;
333+
hw->tl1_per_bgx = true;
334+
break;
335+
}
336+
hw->tl4_cnt = MAX_QUEUES_PER_QSET * pci_sriov_get_totalvfs(nic->pdev);
337+
}
338+
301339
#define BGX0_BLOCK 8
302340
#define BGX1_BLOCK 9
303341

@@ -306,6 +344,9 @@ static void nic_init_hw(struct nicpf *nic)
306344
int i;
307345
u64 cqm_cfg;
308346

347+
/* Get HW capability info */
348+
nic_get_hw_info(nic);
349+
309350
/* Enable NIC HW block */
310351
nic_reg_write(nic, NIC_PF_CFG, 0x3);
311352

@@ -351,6 +392,7 @@ static void nic_init_hw(struct nicpf *nic)
351392
/* Channel parse index configuration */
352393
static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
353394
{
395+
struct hw_info *hw = nic->hw;
354396
u32 vnic, bgx, lmac, chan;
355397
u32 padd, cpi_count = 0;
356398
u64 cpi_base, cpi, rssi_base, rssi;
@@ -360,9 +402,11 @@ static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
360402
bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
361403
lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
362404

363-
chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
364-
cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX);
365-
rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX);
405+
chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
406+
cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) +
407+
(bgx * (hw->cpi_cnt / hw->bgx_cnt));
408+
rssi_base = (lmac * hw->rss_ind_tbl_size) +
409+
(bgx * (hw->rssi_cnt / hw->bgx_cnt));
366410

367411
/* Rx channel configuration */
368412
nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
@@ -434,7 +478,7 @@ static void nic_send_rss_size(struct nicpf *nic, int vf)
434478
msg = (u64 *)&mbx;
435479

436480
mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
437-
mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
481+
mbx.rss_size.ind_tbl_size = nic->hw->rss_ind_tbl_size;
438482
nic_send_msg_to_vf(nic, vf, &mbx);
439483
}
440484

@@ -494,6 +538,7 @@ static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
494538
static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
495539
struct sq_cfg_msg *sq)
496540
{
541+
struct hw_info *hw = nic->hw;
497542
u32 bgx, lmac, chan;
498543
u32 tl2, tl3, tl4;
499544
u32 rr_quantum;
@@ -512,30 +557,38 @@ static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
512557
/* 24 bytes for FCS, IPG and preamble */
513558
rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
514559

560+
/* For 88xx 0-511 TL4 transmits via BGX0 and
561+
* 512-1023 TL4s transmit via BGX1.
562+
*/
563+
tl4 = bgx * (hw->tl4_cnt / hw->bgx_cnt);
515564
if (!sq->sqs_mode) {
516-
tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX);
565+
tl4 += (lmac * MAX_QUEUES_PER_QSET);
517566
} else {
518567
for (svf = 0; svf < MAX_SQS_PER_VF; svf++) {
519568
if (nic->vf_sqs[pqs_vnic][svf] == vnic)
520569
break;
521570
}
522-
tl4 = (MAX_LMAC_PER_BGX * NIC_TL4_PER_LMAC);
523-
tl4 += (lmac * NIC_TL4_PER_LMAC * MAX_SQS_PER_VF);
524-
tl4 += (svf * NIC_TL4_PER_LMAC);
525-
tl4 += (bgx * NIC_TL4_PER_BGX);
571+
tl4 += (MAX_LMAC_PER_BGX * MAX_QUEUES_PER_QSET);
572+
tl4 += (lmac * MAX_QUEUES_PER_QSET * MAX_SQS_PER_VF);
573+
tl4 += (svf * MAX_QUEUES_PER_QSET);
526574
}
527575
tl4 += sq_idx;
528576

529-
tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3);
577+
tl3 = tl4 / (hw->tl4_cnt / hw->tl3_cnt);
530578
nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
531579
((u64)vnic << NIC_QS_ID_SHIFT) |
532580
((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
533581
nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
534582
((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
535583

536584
nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
537-
chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
585+
586+
/* On 88xx 0-127 channels are for BGX0 and
587+
* 127-255 channels for BGX1.
588+
*/
589+
chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
538590
nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
591+
539592
/* Enable backpressure on the channel */
540593
nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
541594

@@ -1008,6 +1061,12 @@ static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10081061
if (!nic)
10091062
return -ENOMEM;
10101063

1064+
nic->hw = devm_kzalloc(dev, sizeof(struct hw_info), GFP_KERNEL);
1065+
if (!nic->hw) {
1066+
devm_kfree(dev, nic);
1067+
return -ENOMEM;
1068+
}
1069+
10111070
pci_set_drvdata(pdev, nic);
10121071

10131072
nic->pdev = pdev;
@@ -1047,13 +1106,10 @@ static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10471106

10481107
nic->node = nic_get_node_id(pdev);
10491108

1050-
nic_set_lmac_vf_mapping(nic);
1051-
10521109
/* Initialize hardware */
10531110
nic_init_hw(nic);
10541111

1055-
/* Set RSS TBL size for each VF */
1056-
nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
1112+
nic_set_lmac_vf_mapping(nic);
10571113

10581114
/* Register interrupts */
10591115
err = nic_register_interrupts(nic);
@@ -1086,6 +1142,8 @@ static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10861142
err_release_regions:
10871143
pci_release_regions(pdev);
10881144
err_disable_device:
1145+
devm_kfree(dev, nic->hw);
1146+
devm_kfree(dev, nic);
10891147
pci_disable_device(pdev);
10901148
pci_set_drvdata(pdev, NULL);
10911149
return err;
@@ -1106,6 +1164,10 @@ static void nic_remove(struct pci_dev *pdev)
11061164

11071165
nic_unregister_interrupts(nic);
11081166
pci_release_regions(pdev);
1167+
1168+
devm_kfree(&pdev->dev, nic->hw);
1169+
devm_kfree(&pdev->dev, nic);
1170+
11091171
pci_disable_device(pdev);
11101172
pci_set_drvdata(pdev, NULL);
11111173
}

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