Skip to content

Commit a6d6786

Browse files
Radha Mohan Chintakuntladavem330
Radha Mohan Chintakuntla
authored and
davem330
committed
net: mdio-octeon: Modify driver to work on both ThunderX and Octeon
This patch modifies the mdio-octeon driver to work on both ThunderX and Octeon SoCs from Cavium Inc. Signed-off-by: Sunil Goutham <sgoutham@cavium.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent 71382bc commit a6d6786

File tree

2 files changed

+111
-21
lines changed

2 files changed

+111
-21
lines changed

‎drivers/net/phy/Kconfig

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -150,13 +150,13 @@ config MDIO_GPIO
150150
will be called mdio-gpio.
151151

152152
config MDIO_OCTEON
153-
tristate "Support for MDIO buses on Octeon SOCs"
154-
depends on CAVIUM_OCTEON_SOC
155-
default y
153+
tristate "Support for MDIO buses on Octeon and ThunderX SOCs"
154+
depends on 64BIT
156155
help
157156

158-
This module provides a driver for the Octeon MDIO busses.
159-
It is required by the Octeon Ethernet device drivers.
157+
This module provides a driver for the Octeon and ThunderX MDIO
158+
busses. It is required by the Octeon and ThunderX ethernet device
159+
drivers.
160160

161161
If in doubt, say Y.
162162

‎drivers/net/phy/mdio-octeon.c

Lines changed: 106 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -7,25 +7,100 @@
77
*/
88

99
#include <linux/platform_device.h>
10+
#include <linux/of_address.h>
1011
#include <linux/of_mdio.h>
1112
#include <linux/delay.h>
1213
#include <linux/module.h>
1314
#include <linux/gfp.h>
1415
#include <linux/phy.h>
1516
#include <linux/io.h>
1617

18+
#ifdef CONFIG_CAVIUM_OCTEON_SOC
1719
#include <asm/octeon/octeon.h>
18-
#include <asm/octeon/cvmx-smix-defs.h>
20+
#endif
1921

20-
#define DRV_VERSION "1.0"
21-
#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
22+
#define DRV_VERSION "1.1"
23+
#define DRV_DESCRIPTION "Cavium Networks Octeon/ThunderX SMI/MDIO driver"
2224

2325
#define SMI_CMD 0x0
2426
#define SMI_WR_DAT 0x8
2527
#define SMI_RD_DAT 0x10
2628
#define SMI_CLK 0x18
2729
#define SMI_EN 0x20
2830

31+
#ifdef __BIG_ENDIAN_BITFIELD
32+
#define OCT_MDIO_BITFIELD_FIELD(field, more) \
33+
field; \
34+
more
35+
36+
#else
37+
#define OCT_MDIO_BITFIELD_FIELD(field, more) \
38+
more \
39+
field;
40+
41+
#endif
42+
43+
union cvmx_smix_clk {
44+
u64 u64;
45+
struct cvmx_smix_clk_s {
46+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
47+
OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
48+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
49+
OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
50+
OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
51+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
52+
OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
53+
OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
54+
OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
55+
OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
56+
;))))))))))
57+
} s;
58+
};
59+
60+
union cvmx_smix_cmd {
61+
u64 u64;
62+
struct cvmx_smix_cmd_s {
63+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
64+
OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
65+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
66+
OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
67+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
68+
OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
69+
;))))))
70+
} s;
71+
};
72+
73+
union cvmx_smix_en {
74+
u64 u64;
75+
struct cvmx_smix_en_s {
76+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
77+
OCT_MDIO_BITFIELD_FIELD(u64 en:1,
78+
;))
79+
} s;
80+
};
81+
82+
union cvmx_smix_rd_dat {
83+
u64 u64;
84+
struct cvmx_smix_rd_dat_s {
85+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
86+
OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
87+
OCT_MDIO_BITFIELD_FIELD(u64 val:1,
88+
OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
89+
;))))
90+
} s;
91+
};
92+
93+
union cvmx_smix_wr_dat {
94+
u64 u64;
95+
struct cvmx_smix_wr_dat_s {
96+
OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
97+
OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
98+
OCT_MDIO_BITFIELD_FIELD(u64 val:1,
99+
OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
100+
;))))
101+
} s;
102+
};
103+
29104
enum octeon_mdiobus_mode {
30105
UNINIT = 0,
31106
C22,
@@ -41,6 +116,21 @@ struct octeon_mdiobus {
41116
int phy_irq[PHY_MAX_ADDR];
42117
};
43118

119+
#ifdef CONFIG_CAVIUM_OCTEON_SOC
120+
static void oct_mdio_writeq(u64 val, u64 addr)
121+
{
122+
cvmx_write_csr(addr, val);
123+
}
124+
125+
static u64 oct_mdio_readq(u64 addr)
126+
{
127+
return cvmx_read_csr(addr);
128+
}
129+
#else
130+
#define oct_mdio_writeq(val, addr) writeq_relaxed(val, (void *)addr)
131+
#define oct_mdio_readq(addr) readq_relaxed((void *)addr)
132+
#endif
133+
44134
static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
45135
enum octeon_mdiobus_mode m)
46136
{
@@ -49,10 +139,10 @@ static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
49139
if (m == p->mode)
50140
return;
51141

52-
smi_clk.u64 = cvmx_read_csr(p->register_base + SMI_CLK);
142+
smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
53143
smi_clk.s.mode = (m == C45) ? 1 : 0;
54144
smi_clk.s.preamble = 1;
55-
cvmx_write_csr(p->register_base + SMI_CLK, smi_clk.u64);
145+
oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
56146
p->mode = m;
57147
}
58148

@@ -67,22 +157,22 @@ static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
67157

68158
smi_wr.u64 = 0;
69159
smi_wr.s.dat = regnum & 0xffff;
70-
cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
160+
oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
71161

72162
regnum = (regnum >> 16) & 0x1f;
73163

74164
smi_cmd.u64 = 0;
75165
smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
76166
smi_cmd.s.phy_adr = phy_id;
77167
smi_cmd.s.reg_adr = regnum;
78-
cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
168+
oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
79169

80170
do {
81171
/* Wait 1000 clocks so we don't saturate the RSL bus
82172
* doing reads.
83173
*/
84174
__delay(1000);
85-
smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
175+
smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
86176
} while (smi_wr.s.pending && --timeout);
87177

88178
if (timeout <= 0)
@@ -114,14 +204,14 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
114204
smi_cmd.s.phy_op = op;
115205
smi_cmd.s.phy_adr = phy_id;
116206
smi_cmd.s.reg_adr = regnum;
117-
cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
207+
oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
118208

119209
do {
120210
/* Wait 1000 clocks so we don't saturate the RSL bus
121211
* doing reads.
122212
*/
123213
__delay(1000);
124-
smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT);
214+
smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
125215
} while (smi_rd.s.pending && --timeout);
126216

127217
if (smi_rd.s.val)
@@ -153,20 +243,20 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
153243

154244
smi_wr.u64 = 0;
155245
smi_wr.s.dat = val;
156-
cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
246+
oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
157247

158248
smi_cmd.u64 = 0;
159249
smi_cmd.s.phy_op = op;
160250
smi_cmd.s.phy_adr = phy_id;
161251
smi_cmd.s.reg_adr = regnum;
162-
cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
252+
oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
163253

164254
do {
165255
/* Wait 1000 clocks so we don't saturate the RSL bus
166256
* doing reads.
167257
*/
168258
__delay(1000);
169-
smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
259+
smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
170260
} while (smi_wr.s.pending && --timeout);
171261

172262
if (timeout <= 0)
@@ -210,7 +300,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
210300

211301
smi_en.u64 = 0;
212302
smi_en.s.en = 1;
213-
cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
303+
oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
214304

215305
bus->mii_bus->priv = bus;
216306
bus->mii_bus->irq = bus->phy_irq;
@@ -234,7 +324,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)
234324
mdiobus_free(bus->mii_bus);
235325
fail:
236326
smi_en.u64 = 0;
237-
cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
327+
oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
238328
return err;
239329
}
240330

@@ -248,7 +338,7 @@ static int octeon_mdiobus_remove(struct platform_device *pdev)
248338
mdiobus_unregister(bus->mii_bus);
249339
mdiobus_free(bus->mii_bus);
250340
smi_en.u64 = 0;
251-
cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
341+
oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
252342
return 0;
253343
}
254344

0 commit comments

Comments
 (0)