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Suzuki K Poulosewildea01
Suzuki K Poulose
authored and
wildea01
committed
arm64: cpufeature: Check availability of AArch32
On ARMv8 support for AArch32 state is optional. Hence it is not safe to check the AArch32 ID registers for sanity, which could lead to false warnings. This patch makes sure that the AArch32 state is implemented before we keep track of the 32bit ID registers. As per ARM ARM (D.1.21.2 - Support for Exception Levels and Execution States, DDI0487A.h), checking the support for AArch32 at EL0 is good enough to check the support for AArch32 (i.e, AArch32 at EL1 => AArch32 at EL0, but not vice versa). Tested-by: Yury Norov <ynorov@caviumnetworks.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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‎arch/arm64/kernel/cpufeature.c

Lines changed: 47 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -439,22 +439,26 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
439439
init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
440440
init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
441441
init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
442-
init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
443-
init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
444-
init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
445-
init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
446-
init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
447-
init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
448-
init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
449-
init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
450-
init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
451-
init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
452-
init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
453-
init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
454-
init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
455-
init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
456-
init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
457-
init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
442+
443+
if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
444+
init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
445+
init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
446+
init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
447+
init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
448+
init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
449+
init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
450+
init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
451+
init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
452+
init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
453+
init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
454+
init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
455+
init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
456+
init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
457+
init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
458+
init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
459+
init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
460+
}
461+
458462
}
459463

460464
static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
@@ -559,47 +563,51 @@ void update_cpu_features(int cpu,
559563
info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
560564

561565
/*
562-
* If we have AArch32, we care about 32-bit features for compat. These
563-
* registers should be RES0 otherwise.
566+
* If we have AArch32, we care about 32-bit features for compat.
567+
* If the system doesn't support AArch32, don't update them.
564568
*/
565-
taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
569+
if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&
570+
id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
571+
572+
taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
566573
info->reg_id_dfr0, boot->reg_id_dfr0);
567-
taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
574+
taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
568575
info->reg_id_isar0, boot->reg_id_isar0);
569-
taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
576+
taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
570577
info->reg_id_isar1, boot->reg_id_isar1);
571-
taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
578+
taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
572579
info->reg_id_isar2, boot->reg_id_isar2);
573-
taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
580+
taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
574581
info->reg_id_isar3, boot->reg_id_isar3);
575-
taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
582+
taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
576583
info->reg_id_isar4, boot->reg_id_isar4);
577-
taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
584+
taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
578585
info->reg_id_isar5, boot->reg_id_isar5);
579586

580-
/*
581-
* Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
582-
* ACTLR formats could differ across CPUs and therefore would have to
583-
* be trapped for virtualization anyway.
584-
*/
585-
taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
587+
/*
588+
* Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
589+
* ACTLR formats could differ across CPUs and therefore would have to
590+
* be trapped for virtualization anyway.
591+
*/
592+
taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
586593
info->reg_id_mmfr0, boot->reg_id_mmfr0);
587-
taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
594+
taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
588595
info->reg_id_mmfr1, boot->reg_id_mmfr1);
589-
taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
596+
taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
590597
info->reg_id_mmfr2, boot->reg_id_mmfr2);
591-
taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
598+
taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
592599
info->reg_id_mmfr3, boot->reg_id_mmfr3);
593-
taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
600+
taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
594601
info->reg_id_pfr0, boot->reg_id_pfr0);
595-
taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
602+
taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
596603
info->reg_id_pfr1, boot->reg_id_pfr1);
597-
taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
604+
taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
598605
info->reg_mvfr0, boot->reg_mvfr0);
599-
taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
606+
taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
600607
info->reg_mvfr1, boot->reg_mvfr1);
601-
taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
608+
taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
602609
info->reg_mvfr2, boot->reg_mvfr2);
610+
}
603611

604612
/*
605613
* Mismatched CPU features are a recipe for disaster. Don't even

‎arch/arm64/kernel/cpuinfo.c

Lines changed: 20 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -216,23 +216,26 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
216216
info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
217217
info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
218218

219-
info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
220-
info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
221-
info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
222-
info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
223-
info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
224-
info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
225-
info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
226-
info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
227-
info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
228-
info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
229-
info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
230-
info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
231-
info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
232-
233-
info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
234-
info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
235-
info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
219+
/* Update the 32bit ID registers only if AArch32 is implemented */
220+
if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
221+
info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
222+
info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
223+
info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
224+
info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
225+
info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
226+
info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
227+
info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
228+
info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
229+
info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
230+
info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
231+
info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
232+
info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
233+
info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
234+
235+
info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
236+
info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
237+
info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
238+
}
236239

237240
cpuinfo_detect_icache_policy(info);
238241

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