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Merge tag 'drm-intel-next-2017-05-29' of git://anongit.freedesktop.org/git/drm-intel into drm-next
More stuff for 4.13: - skl+ wm fixes from Mahesh Kumar - some refactor and tests for i915_sw_fence (Chris) - tune execlist/scheduler code (Chris) - g4x,g33 gpu reset improvements (Chris, Mika) - guc code cleanup (Michal Wajdeczko, Michał Winiarski) - dp aux backlight improvements (Puthikorn Voravootivat) - buffer based guc/host communication (Michal Wajdeczko) * tag 'drm-intel-next-2017-05-29' of git://anongit.freedesktop.org/git/drm-intel: (253 commits) drm/i915: Update DRIVER_DATE to 20170529 drm/i915: Keep the forcewake timer alive for 1ms past the most recent use drm/i915/guc: capture GuC logs if FW fails to load drm/i915/guc: Introduce buffer based cmd transport drm/i915/guc: Disable send function on fini drm: Add definition for eDP backlight frequency drm/i915: Drop AUX backlight enable check for backlight control drm/i915: Consolidate #ifdef CONFIG_INTEL_IOMMU drm/i915: Only GGTT vma may be pinned and prevent shrinking drm/i915: Serialize GTT/Aperture accesses on BXT drm/i915: Convert i915_gem_object_ops->flags values to use BIT() drm/i915/selftests: Silence compiler warning in igt_ctx_exec drm/i915/guc: Skip port assign on first iteration of GuC dequeue drm/i915: Remove misleading comment in request_alloc drm/i915/g33: Improve reset reliability Revert "drm/i915: Restore lost "Initialized i915" welcome message" drm/i915/huc: Update GLK HuC version drm/i915: Check for allocation failure drm/i915/guc: Remove action status and statistics from debugfs drm/i915/g4x: Improve gpu reset reliability ...
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‎drivers/gpu/drm/i915/Kconfig.debug

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,18 @@ config DRM_I915_SW_FENCE_DEBUG_OBJECTS
6161

6262
If in doubt, say "N".
6363

64+
config DRM_I915_SW_FENCE_CHECK_DAG
65+
bool "Enable additional driver debugging for detecting dependency cycles"
66+
depends on DRM_I915
67+
default n
68+
help
69+
Choose this option to turn on extra driver debugging that may affect
70+
performance but will catch some internal issues.
71+
72+
Recommended for driver developers only.
73+
74+
If in doubt, say "N".
75+
6476
config DRM_I915_SELFTEST
6577
bool "Enable selftests upon driver load"
6678
depends on DRM_I915

‎drivers/gpu/drm/i915/Makefile

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ i915-y := i915_drv.o \
1616
i915_params.o \
1717
i915_pci.o \
1818
i915_suspend.o \
19+
i915_syncmap.o \
1920
i915_sw_fence.o \
2021
i915_sysfs.o \
2122
intel_csr.o \
@@ -57,6 +58,7 @@ i915-y += i915_cmd_parser.o \
5758

5859
# general-purpose microcontroller (GuC) support
5960
i915-y += intel_uc.o \
61+
intel_guc_ct.o \
6062
intel_guc_log.o \
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intel_guc_loader.o \
6264
intel_huc.o \

‎drivers/gpu/drm/i915/dvo_ch7017.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -280,10 +280,10 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo,
280280
(0 << CH7017_PHASE_DETECTOR_SHIFT);
281281
} else {
282282
outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_HIGH;
283-
lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |
283+
lvds_pll_feedback_div =
284+
CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |
284285
(2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) |
285286
(3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT);
286-
lvds_pll_feedback_div = 35;
287287
lvds_control_2 = (3 << CH7017_LOOP_FILTER_SHIFT) |
288288
(0 << CH7017_PHASE_DETECTOR_SHIFT);
289289
if (1) { /* XXX: dual channel panel detection. Assume yes for now. */

‎drivers/gpu/drm/i915/gvt/scheduler.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -69,8 +69,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
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gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
7070
workload->ctx_desc.lrca);
7171

72-
context_page_num = intel_lr_context_size(
73-
gvt->dev_priv->engine[ring_id]);
72+
context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
7473

7574
context_page_num = context_page_num >> PAGE_SHIFT;
7675

@@ -181,6 +180,7 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
181180
struct intel_engine_cs *engine = dev_priv->engine[ring_id];
182181
struct drm_i915_gem_request *rq;
183182
struct intel_vgpu *vgpu = workload->vgpu;
183+
struct intel_ring *ring;
184184
int ret;
185185

186186
gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
@@ -199,8 +199,9 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
199199
* shadow_ctx pages invalid. So gvt need to pin itself. After update
200200
* the guest context, gvt can unpin the shadow_ctx safely.
201201
*/
202-
ret = engine->context_pin(engine, shadow_ctx);
203-
if (ret) {
202+
ring = engine->context_pin(engine, shadow_ctx);
203+
if (IS_ERR(ring)) {
204+
ret = PTR_ERR(ring);
204205
gvt_vgpu_err("fail to pin shadow context\n");
205206
workload->status = ret;
206207
mutex_unlock(&dev_priv->drm.struct_mutex);
@@ -330,8 +331,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
330331
gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
331332
workload->ctx_desc.lrca);
332333

333-
context_page_num = intel_lr_context_size(
334-
gvt->dev_priv->engine[ring_id]);
334+
context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
335335

336336
context_page_num = context_page_num >> PAGE_SHIFT;
337337

‎drivers/gpu/drm/i915/i915_cmd_parser.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1166,8 +1166,8 @@ static bool check_cmd(const struct intel_engine_cs *engine,
11661166
find_reg(engine, is_master, reg_addr);
11671167

11681168
if (!reg) {
1169-
DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (exec_id=%d)\n",
1170-
reg_addr, *cmd, engine->exec_id);
1169+
DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
1170+
reg_addr, *cmd, engine->name);
11711171
return false;
11721172
}
11731173

@@ -1222,11 +1222,11 @@ static bool check_cmd(const struct intel_engine_cs *engine,
12221222
desc->bits[i].mask;
12231223

12241224
if (dword != desc->bits[i].expected) {
1225-
DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (exec_id=%d)\n",
1225+
DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
12261226
*cmd,
12271227
desc->bits[i].mask,
12281228
desc->bits[i].expected,
1229-
dword, engine->exec_id);
1229+
dword, engine->name);
12301230
return false;
12311231
}
12321232
}
@@ -1284,7 +1284,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
12841284

12851285
if (*cmd == MI_BATCH_BUFFER_END) {
12861286
if (needs_clflush_after) {
1287-
void *ptr = ptr_mask_bits(shadow_batch_obj->mm.mapping);
1287+
void *ptr = page_mask_bits(shadow_batch_obj->mm.mapping);
12881288
drm_clflush_virt_range(ptr,
12891289
(void *)(cmd + 1) - ptr);
12901290
}

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