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Uwe Kleine-König
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ARM: imx: change static io mapping to use a function
Now only the virtual addresses [0xf4000000, 0xf5ffffff] are used for static per-SoC mappings. The few mappings of whole chip selects are moved accordingly. The now wrong defines for virtual base addresses are removed. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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11 files changed

+89
-208
lines changed

11 files changed

+89
-208
lines changed

‎arch/arm/plat-mxc/include/mach/hardware.h

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,73 @@
3232
(((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
3333
(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
3434

35+
/*
36+
* This is rather complicated for humans and ugly to verify, but for a machine
37+
* it's OK. Still more as it is usually only applied to constants. The upsides
38+
* on using this approach are:
39+
*
40+
* - same mapping on all i.MX machines
41+
* - works for assembler, too
42+
* - no need to nurture #defines for virtual addresses
43+
*
44+
* The downside it, it's hard to verify (but I have a script for that).
45+
*
46+
* Obviously this needs to be injective for each SoC. In general it maps the
47+
* whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
48+
* is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
49+
*
50+
* It applies the following mappings for the different SoCs:
51+
*
52+
* mx1:
53+
* IO 0x00200000+0x100000 -> 0xf4000000+0x100000
54+
* mx21:
55+
* AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
56+
* SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
57+
* X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
58+
* mx25:
59+
* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
60+
* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
61+
* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
62+
* mx27:
63+
* AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
64+
* SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
65+
* X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
66+
* mx31:
67+
* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
68+
* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
69+
* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
70+
* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
71+
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
72+
* mx35:
73+
* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
74+
* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
75+
* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
76+
* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
77+
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
78+
* mx51:
79+
* IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
80+
* DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
81+
* SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
82+
* AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
83+
* AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
84+
* mxc91231:
85+
* L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
86+
* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
87+
* ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
88+
* AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
89+
* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
90+
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
91+
* SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
92+
* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
93+
*/
94+
#define IMX_IO_P2V(x) ( \
95+
0xf4000000 + \
96+
(((x) & 0x50000000) >> 6) + \
97+
(((x) & 0x0b000000) >> 4) + \
98+
(((x) & 0x000fffff)))
99+
100+
#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
101+
35102
#ifdef CONFIG_ARCH_MX5
36103
#include <mach/mx51.h>
37104
#endif

‎arch/arm/plat-mxc/include/mach/mx1.h

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@
1919
*/
2020
#define MX1_IO_BASE_ADDR 0x00200000
2121
#define MX1_IO_SIZE SZ_1M
22-
#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
2322

2423
#define MX1_CS0_PHYS 0x10000000
2524
#define MX1_CS0_SIZE 0x02000000
@@ -73,8 +72,7 @@
7372
#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
7473

7574
/* macro to get at IO space when running virtually */
76-
#define MX1_IO_P2V(x) ( \
77-
IMX_IO_P2V_MODULE(x, MX1_IO))
75+
#define MX1_IO_P2V(x) IMX_IO_P2V(x)
7876
#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
7977

8078
/* fixed interrput numbers */
@@ -171,7 +169,6 @@
171169
/* these should go away */
172170
#define IMX_IO_PHYS MX1_IO_BASE_ADDR
173171
#define IMX_IO_SIZE MX1_IO_SIZE
174-
#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
175172
#define IMX_CS0_PHYS MX1_CS0_PHYS
176173
#define IMX_CS0_SIZE MX1_CS0_SIZE
177174
#define IMX_CS1_PHYS MX1_CS1_PHYS

‎arch/arm/plat-mxc/include/mach/mx21.h

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@
2626
#define __MACH_MX21_H__
2727

2828
#define MX21_AIPI_BASE_ADDR 0x10000000
29-
#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
3029
#define MX21_AIPI_SIZE SZ_1M
3130
#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
3231
#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
@@ -64,7 +63,6 @@
6463
#define MX21_AVIC_BASE_ADDR 0x10040000
6564

6665
#define MX21_SAHB1_BASE_ADDR 0x80000000
67-
#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
6866
#define MX21_SAHB1_SIZE SZ_1M
6967
#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
7068

@@ -82,7 +80,6 @@
8280

8381
/* NAND, SDRAM, WEIM etc controllers */
8482
#define MX21_X_MEMC_BASE_ADDR 0xdf000000
85-
#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
8683
#define MX21_X_MEMC_SIZE SZ_256K
8784

8885
#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
@@ -92,10 +89,7 @@
9289

9390
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
9491

95-
#define MX21_IO_P2V(x) ( \
96-
IMX_IO_P2V_MODULE(x, MX21_AIPI) ?: \
97-
IMX_IO_P2V_MODULE(x, MX21_SAHB1) ?: \
98-
IMX_IO_P2V_MODULE(x, MX21_X_MEMC))
92+
#define MX21_IO_P2V(x) IMX_IO_P2V(x)
9993
#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
10094

10195
/* fixed interrupt numbers */
@@ -197,7 +191,6 @@
197191
#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
198192
#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
199193
#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
200-
#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
201194
#define X_MEMC_SIZE MX21_X_MEMC_SIZE
202195
#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
203196
#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR

‎arch/arm/plat-mxc/include/mach/mx25.h

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,11 @@
22
#define __MACH_MX25_H__
33

44
#define MX25_AIPS1_BASE_ADDR 0x43f00000
5-
#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
5+
#define MX25_AIPS1_BASE_ADDR_VIRT 0xf5300000
66
#define MX25_AIPS1_SIZE SZ_1M
77
#define MX25_AIPS2_BASE_ADDR 0x53f00000
8-
#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
98
#define MX25_AIPS2_SIZE SZ_1M
109
#define MX25_AVIC_BASE_ADDR 0x68000000
11-
#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
1210
#define MX25_AVIC_SIZE SZ_1M
1311

1412
#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
@@ -27,12 +25,6 @@
2725
#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
2826
#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
2927

30-
#define MX25_IO_P2V(x) ( \
31-
IMX_IO_P2V_MODULE(x, MX25_AIPS1) ?: \
32-
IMX_IO_P2V_MODULE(x, MX25_AIPS2) ?: \
33-
IMX_IO_P2V_MODULE(x, MX25_AVIC))
34-
#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
35-
3628
#define MX25_AIPS1_IO_ADDRESS(x) \
3729
(((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
3830

@@ -58,6 +50,9 @@
5850
#define MX25_OTG_BASE_ADDR 0x53ff4000
5951
#define MX25_CSI_BASE_ADDR 0x53ff8000
6052

53+
#define MX25_IO_P2V(x) IMX_IO_P2V(x)
54+
#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
55+
6156
#define MX25_INT_CSPI3 0
6257
#define MX25_INT_I2C1 3
6358
#define MX25_INT_I2C2 4

‎arch/arm/plat-mxc/include/mach/mx27.h

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@
2929
#endif
3030

3131
#define MX27_AIPI_BASE_ADDR 0x10000000
32-
#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
3332
#define MX27_AIPI_SIZE SZ_1M
3433
#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
3534
#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
@@ -87,7 +86,6 @@
8786
#define MX27_ROMP_BASE_ADDR 0x10041000
8887

8988
#define MX27_SAHB1_BASE_ADDR 0x80000000
90-
#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
9189
#define MX27_SAHB1_SIZE SZ_1M
9290
#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
9391
#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
@@ -105,7 +103,6 @@
105103

106104
/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
107105
#define MX27_X_MEMC_BASE_ADDR 0xd8000000
108-
#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
109106
#define MX27_X_MEMC_SIZE SZ_1M
110107
#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
111108
#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
@@ -123,10 +120,7 @@
123120
/* IRAM */
124121
#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
125122

126-
#define MX27_IO_P2V(x) ( \
127-
IMX_IO_P2V_MODULE(x, MX27_AIPI) ?: \
128-
IMX_IO_P2V_MODULE(x, MX27_SAHB1) ?: \
129-
IMX_IO_P2V_MODULE(x, MX27_X_MEMC))
123+
#define MX27_IO_P2V(x) IMX_IO_P2V(x)
130124
#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
131125

132126
#ifndef __ASSEMBLER__
@@ -280,7 +274,6 @@ extern int mx27_revision(void);
280274
#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
281275
#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
282276
#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
283-
#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
284277
#define X_MEMC_SIZE MX27_X_MEMC_SIZE
285278
#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
286279
#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR

‎arch/arm/plat-mxc/include/mach/mx2x.h

Lines changed: 2 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727

2828
/* Register offsets */
2929
#define MX2x_AIPI_BASE_ADDR 0x10000000
30-
#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
30+
#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4400000
3131
#define MX2x_AIPI_SIZE SZ_1M
3232
#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
3333
#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
@@ -65,43 +65,12 @@
6565
#define MX2x_AVIC_BASE_ADDR 0x10040000
6666

6767
#define MX2x_SAHB1_BASE_ADDR 0x80000000
68-
#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
6968
#define MX2x_SAHB1_SIZE SZ_1M
7069
#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
7170

72-
/*
73-
* This macro defines the physical to virtual address mapping for all the
74-
* peripheral modules. It is used by passing in the physical address as x
75-
* and returning the virtual address. If the physical address is not mapped,
76-
* it returns 0xDEADBEEF
77-
*/
78-
#define IO_ADDRESS(x) \
79-
(void __force __iomem *) \
80-
(((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
81-
AIPI_IO_ADDRESS(x) : \
82-
((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
83-
SAHB1_IO_ADDRESS(x) : \
84-
((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
85-
X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
86-
87-
/* define the address mapping macros: in physical address order */
88-
#define AIPI_IO_ADDRESS(x) \
71+
#define AIPI_IO_ADDRESS(x) \
8972
(((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
9073

91-
#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
92-
93-
#define SAHB1_IO_ADDRESS(x) \
94-
(((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
95-
96-
#define CS4_IO_ADDRESS(x) \
97-
(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
98-
99-
#define X_MEMC_IO_ADDRESS(x) \
100-
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
101-
102-
#define PCMCIA_IO_ADDRESS(x) \
103-
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
104-
10574
/* fixed interrupt numbers */
10675
#define MX2x_INT_CSPI3 6
10776
#define MX2x_INT_GPIO 8
@@ -215,7 +184,6 @@
215184
#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
216185
#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
217186
#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
218-
#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
219187
#define SAHB1_SIZE MX2x_SAHB1_SIZE
220188
#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
221189
#define MXC_INT_CSPI3 MX2x_INT_CSPI3

‎arch/arm/plat-mxc/include/mach/mx31.h

Lines changed: 3 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@
1515
#define MX31_L2CC_SIZE SZ_1M
1616

1717
#define MX31_AIPS1_BASE_ADDR 0x43f00000
18-
#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
1918
#define MX31_AIPS1_SIZE SZ_1M
2019
#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
2120
#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
@@ -41,7 +40,6 @@
4140
#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
4241

4342
#define MX31_SPBA0_BASE_ADDR 0x50000000
44-
#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
4543
#define MX31_SPBA0_SIZE SZ_1M
4644
#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
4745
#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
@@ -55,7 +53,6 @@
5553
#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
5654

5755
#define MX31_AIPS2_BASE_ADDR 0x53f00000
58-
#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
5956
#define MX31_AIPS2_SIZE SZ_1M
6057
#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
6158
#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
@@ -84,7 +81,6 @@
8481
#define MX31_ROMP_SIZE SZ_1M
8582

8683
#define MX31_AVIC_BASE_ADDR 0x68000000
87-
#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
8884
#define MX31_AVIC_SIZE SZ_1M
8985

9086
#define MX31_IPU_MEM_BASE_ADDR 0x70000000
@@ -97,15 +93,14 @@
9793
#define MX31_CS3_BASE_ADDR 0xb2000000
9894

9995
#define MX31_CS4_BASE_ADDR 0xb4000000
100-
#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000
96+
#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000
10197
#define MX31_CS4_SIZE SZ_32M
10298

10399
#define MX31_CS5_BASE_ADDR 0xb6000000
104-
#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000
100+
#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000
105101
#define MX31_CS5_SIZE SZ_32M
106102

107103
#define MX31_X_MEMC_BASE_ADDR 0xb8000000
108-
#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
109104
#define MX31_X_MEMC_SIZE SZ_64K
110105
#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
111106
#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
@@ -121,12 +116,7 @@
121116

122117
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
123118

124-
#define MX31_IO_P2V(x) ( \
125-
IMX_IO_P2V_MODULE(x, MX31_AIPS1) ?: \
126-
IMX_IO_P2V_MODULE(x, MX31_AIPS2) ?: \
127-
IMX_IO_P2V_MODULE(x, MX31_AVIC) ?: \
128-
IMX_IO_P2V_MODULE(x, MX31_X_MEMC) ?: \
129-
IMX_IO_P2V_MODULE(x, MX31_SPBA0))
119+
#define MX31_IO_P2V(x) IMX_IO_P2V(x)
130120
#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
131121

132122
#ifndef __ASSEMBLER__

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