@@ -369,7 +369,7 @@ EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
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static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT (0 );
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- static void erratum_set_next_event_tval_generic (const int access , unsigned long evt ,
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+ static void erratum_set_next_event_generic (const int access , unsigned long evt ,
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struct clock_event_device * clk )
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{
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unsigned long ctrl ;
@@ -390,17 +390,17 @@ static void erratum_set_next_event_tval_generic(const int access, unsigned long
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arch_timer_reg_write (access , ARCH_TIMER_REG_CTRL , ctrl , clk );
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}
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- static __maybe_unused int erratum_set_next_event_tval_virt (unsigned long evt ,
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+ static __maybe_unused int erratum_set_next_event_virt (unsigned long evt ,
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struct clock_event_device * clk )
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{
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- erratum_set_next_event_tval_generic (ARCH_TIMER_VIRT_ACCESS , evt , clk );
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+ erratum_set_next_event_generic (ARCH_TIMER_VIRT_ACCESS , evt , clk );
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return 0 ;
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}
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- static __maybe_unused int erratum_set_next_event_tval_phys (unsigned long evt ,
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+ static __maybe_unused int erratum_set_next_event_phys (unsigned long evt ,
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struct clock_event_device * clk )
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{
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- erratum_set_next_event_tval_generic (ARCH_TIMER_PHYS_ACCESS , evt , clk );
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+ erratum_set_next_event_generic (ARCH_TIMER_PHYS_ACCESS , evt , clk );
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return 0 ;
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}
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@@ -412,8 +412,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
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.desc = "Freescale erratum a005858" ,
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.read_cntpct_el0 = fsl_a008585_read_cntpct_el0 ,
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.read_cntvct_el0 = fsl_a008585_read_cntvct_el0 ,
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- .set_next_event_phys = erratum_set_next_event_tval_phys ,
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- .set_next_event_virt = erratum_set_next_event_tval_virt ,
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+ .set_next_event_phys = erratum_set_next_event_phys ,
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+ .set_next_event_virt = erratum_set_next_event_virt ,
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},
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#endif
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#ifdef CONFIG_HISILICON_ERRATUM_161010101
@@ -423,17 +423,17 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
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.desc = "HiSilicon erratum 161010101" ,
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.read_cntpct_el0 = hisi_161010101_read_cntpct_el0 ,
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.read_cntvct_el0 = hisi_161010101_read_cntvct_el0 ,
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- .set_next_event_phys = erratum_set_next_event_tval_phys ,
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- .set_next_event_virt = erratum_set_next_event_tval_virt ,
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+ .set_next_event_phys = erratum_set_next_event_phys ,
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+ .set_next_event_virt = erratum_set_next_event_virt ,
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},
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{
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.match_type = ate_match_acpi_oem_info ,
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.id = hisi_161010101_oem_info ,
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.desc = "HiSilicon erratum 161010101" ,
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.read_cntpct_el0 = hisi_161010101_read_cntpct_el0 ,
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.read_cntvct_el0 = hisi_161010101_read_cntvct_el0 ,
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- .set_next_event_phys = erratum_set_next_event_tval_phys ,
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- .set_next_event_virt = erratum_set_next_event_tval_virt ,
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+ .set_next_event_phys = erratum_set_next_event_phys ,
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+ .set_next_event_virt = erratum_set_next_event_virt ,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_858921
@@ -452,8 +452,8 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
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.desc = "Allwinner erratum UNKNOWN1" ,
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.read_cntpct_el0 = sun50i_a64_read_cntpct_el0 ,
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.read_cntvct_el0 = sun50i_a64_read_cntvct_el0 ,
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- .set_next_event_phys = erratum_set_next_event_tval_phys ,
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- .set_next_event_virt = erratum_set_next_event_tval_virt ,
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+ .set_next_event_phys = erratum_set_next_event_phys ,
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+ .set_next_event_virt = erratum_set_next_event_virt ,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1418040
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